add tinygo device files

targets/device/nxp/lpc1102_04.s

@@ -0,0 +1,117 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC1102_4_v4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC1102/04
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIO0_0_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long PIO0_8_IRQHandler
+    .long PIO0_9_IRQHandler
+    .long PIO0_10_IRQHandler
+    .long PIO0_11_IRQHandler
+    .long PIO1_0_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SPI0_IRQHandler
+    .long UART_IRQHandler
+    .long 0
+    .long 0
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long FMC_IRQHandler
+    .long 0
+    .long 0
+    .long GPIO1_IRQHandler
+    .long GPIO0_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIO0_0_IRQHandler
+    IRQ PIO0_8_IRQHandler
+    IRQ PIO0_9_IRQHandler
+    IRQ PIO0_10_IRQHandler
+    IRQ PIO0_11_IRQHandler
+    IRQ PIO1_0_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ UART_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ FMC_IRQHandler
+    IRQ GPIO1_IRQHandler
+    IRQ GPIO0_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc111x_lpc11cxx.s

@@ -0,0 +1,129 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11xx_v6a.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11xx, LPC11Cxx, LPC11xxL, LPC11xxXL
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIO0_0_IRQHandler
+    .long PIO0_1_IRQHandler
+    .long PIO0_2_IRQHandler
+    .long PIO0_3_IRQHandler
+    .long PIO0_4_IRQHandler
+    .long PIO0_5_IRQHandler
+    .long PIO0_6_IRQHandler
+    .long PIO0_7_IRQHandler
+    .long PIO0_8_IRQHandler
+    .long PIO0_9_IRQHandler
+    .long PIO0_10_IRQHandler
+    .long PIO0_11_IRQHandler
+    .long PIO1_0_IRQHandler
+    .long C_CAN_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SPI0_IRQHandler
+    .long UART_IRQHandler
+    .long 0
+    .long 0
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long FMC_IRQHandler
+    .long GPIO3_IRQHandler
+    .long GPIO2_IRQHandler
+    .long GPIO1_IRQHandler
+    .long GPIO0_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIO0_0_IRQHandler
+    IRQ PIO0_1_IRQHandler
+    IRQ PIO0_2_IRQHandler
+    IRQ PIO0_3_IRQHandler
+    IRQ PIO0_4_IRQHandler
+    IRQ PIO0_5_IRQHandler
+    IRQ PIO0_6_IRQHandler
+    IRQ PIO0_7_IRQHandler
+    IRQ PIO0_8_IRQHandler
+    IRQ PIO0_9_IRQHandler
+    IRQ PIO0_10_IRQHandler
+    IRQ PIO0_11_IRQHandler
+    IRQ PIO1_0_IRQHandler
+    IRQ C_CAN_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ UART_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ FMC_IRQHandler
+    IRQ GPIO3_IRQHandler
+    IRQ GPIO2_IRQHandler
+    IRQ GPIO1_IRQHandler
+    IRQ GPIO0_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc11axx.s

@@ -0,0 +1,131 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11Axxv0.6.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11Axx
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long CMP_IRQHandler
+    .long DAC_IRQHandler
+    .long RESERVED0_IRQHandler
+    .long RESERVED1_IRQHandler
+    .long SSP1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SSP0_IRQHandler
+    .long USART_IRQHandler
+    .long RESERVED2_IRQHandler
+    .long RESERVED3_IRQHandler
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long FMC_IRQHandler
+    .long RESERVED4_IRQHandler
+    .long RESERVED5_IRQHandler
+    .long RESERVED6_IRQHandler
+    .long RESERVED7_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ CMP_IRQHandler
+    IRQ DAC_IRQHandler
+    IRQ RESERVED0_IRQHandler
+    IRQ RESERVED1_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ USART_IRQHandler
+    IRQ RESERVED2_IRQHandler
+    IRQ RESERVED3_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ FMC_IRQHandler
+    IRQ RESERVED4_IRQHandler
+    IRQ RESERVED5_IRQHandler
+    IRQ RESERVED6_IRQHandler
+    IRQ RESERVED7_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc11cxx.s

@@ -0,0 +1,129 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11Cxx_v9.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11Cxx
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIO0_0_IRQHandler
+    .long PIO0_1_IRQHandler
+    .long PIO0_2_IRQHandler
+    .long PIO0_3_IRQHandler
+    .long PIO0_4_IRQHandler
+    .long PIO0_5_IRQHandler
+    .long PIO0_6_IRQHandler
+    .long PIO0_7_IRQHandler
+    .long PIO0_8_IRQHandler
+    .long PIO0_9_IRQHandler
+    .long PIO0_10_IRQHandler
+    .long PIO0_11_IRQHandler
+    .long PIO1_0_IRQHandler
+    .long C_CAN_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SPI0_IRQHandler
+    .long UART_IRQHandler
+    .long 0
+    .long 0
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long FMC_IRQHandler
+    .long GPIO3_IRQHandler
+    .long GPIO2_IRQHandler
+    .long GPIO1_IRQHandler
+    .long GPIO0_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIO0_0_IRQHandler
+    IRQ PIO0_1_IRQHandler
+    IRQ PIO0_2_IRQHandler
+    IRQ PIO0_3_IRQHandler
+    IRQ PIO0_4_IRQHandler
+    IRQ PIO0_5_IRQHandler
+    IRQ PIO0_6_IRQHandler
+    IRQ PIO0_7_IRQHandler
+    IRQ PIO0_8_IRQHandler
+    IRQ PIO0_9_IRQHandler
+    IRQ PIO0_10_IRQHandler
+    IRQ PIO0_11_IRQHandler
+    IRQ PIO1_0_IRQHandler
+    IRQ C_CAN_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ UART_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ FMC_IRQHandler
+    IRQ GPIO3_IRQHandler
+    IRQ GPIO2_IRQHandler
+    IRQ GPIO1_IRQHandler
+    IRQ GPIO0_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc11d14.s

@@ -0,0 +1,128 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11D14_svd_v4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11D14
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIO0_0_IRQHandler
+    .long PIO0_1_IRQHandler
+    .long PIO0_2_IRQHandler
+    .long PIO0_3_IRQHandler
+    .long PIO0_4_IRQHandler
+    .long PIO0_5_IRQHandler
+    .long PIO0_6_IRQHandler
+    .long PIO0_7_IRQHandler
+    .long PIO0_8_IRQHandler
+    .long PIO0_9_IRQHandler
+    .long PIO0_10_IRQHandler
+    .long PIO0_11_IRQHandler
+    .long PIO1_0_IRQHandler
+    .long 0
+    .long SPI1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SPI0_IRQHandler
+    .long UART_IRQHandler
+    .long 0
+    .long 0
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long FMC_IRQHandler
+    .long GPIO3_IRQHandler
+    .long GPIO2_IRQHandler
+    .long GPIO1_IRQHandler
+    .long GPIO0_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIO0_0_IRQHandler
+    IRQ PIO0_1_IRQHandler
+    IRQ PIO0_2_IRQHandler
+    IRQ PIO0_3_IRQHandler
+    IRQ PIO0_4_IRQHandler
+    IRQ PIO0_5_IRQHandler
+    IRQ PIO0_6_IRQHandler
+    IRQ PIO0_7_IRQHandler
+    IRQ PIO0_8_IRQHandler
+    IRQ PIO0_9_IRQHandler
+    IRQ PIO0_10_IRQHandler
+    IRQ PIO0_11_IRQHandler
+    IRQ PIO1_0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ UART_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ FMC_IRQHandler
+    IRQ GPIO3_IRQHandler
+    IRQ GPIO2_IRQHandler
+    IRQ GPIO1_IRQHandler
+    IRQ GPIO0_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc11e6x.s

@@ -0,0 +1,123 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11E6x_v0.8.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11E6x ARM cortex-m0+
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long I2C1_IRQHandler
+    .long USART1_4_IRQHandler
+    .long USART2_3_IRQHandler
+    .long SCT0_1_IRQHandler
+    .long SSP1_IRQHandler
+    .long I2C0_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SSP0_IRQHandler
+    .long USART_IRQHandler
+    .long 0
+    .long 0
+    .long ADC_A_IRQHandler
+    .long RTC_IRQHandler
+    .long BOD_WDT_IRQHandler
+    .long FLASH_IRQHandler
+    .long DMA_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ USART1_4_IRQHandler
+    IRQ USART2_3_IRQHandler
+    IRQ SCT0_1_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ USART_IRQHandler
+    IRQ ADC_A_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ BOD_WDT_IRQHandler
+    IRQ FLASH_IRQHandler
+    IRQ DMA_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc11exx.s

@@ -0,0 +1,116 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11Exx_v5.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11Exx 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USART
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SSP1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SSP0_IRQHandler
+    .long USART_IRQHandler
+    .long 0
+    .long 0
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long 0
+    .long FLASH_IRQ_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ USART_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ FLASH_IRQ_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc11uxx.s

@@ -0,0 +1,123 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC11Uxx_v7.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC11Uxx
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SSP1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SSP0_IRQHandler
+    .long USART_IRQHandler
+    .long USB_IRQ_IRQHandler
+    .long USB_FIQ_IRQHandler
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQ_IRQHandler
+    .long FLASH_IRQ_IRQHandler
+    .long 0
+    .long 0
+    .long USBWAKEUP_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ USART_IRQHandler
+    IRQ USB_IRQ_IRQHandler
+    IRQ USB_FIQ_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQ_IRQHandler
+    IRQ FLASH_IRQ_IRQHandler
+    IRQ USBWAKEUP_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc13uxx.s

@@ -0,0 +1,124 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC13Uxx_v1.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC1315/16/17/35/36/37 Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long 0
+    .long 0
+    .long RIT_IRQ_IRQHandler
+    .long 0
+    .long SSP1_IRQHandler
+    .long I2C_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SSP0_IRQHandler
+    .long USART_IRQHandler
+    .long USB_IRQ_IRQHandler
+    .long USB_FIQ_IRQHandler
+    .long ADC_IRQHandler
+    .long WWDT_IRQHandler
+    .long BOD_IRQ_IRQHandler
+    .long FLASH_IRQ_IRQHandler
+    .long 0
+    .long 0
+    .long USBWAKEUP_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ RIT_IRQ_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ USART_IRQHandler
+    IRQ USB_IRQ_IRQHandler
+    IRQ USB_FIQ_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WWDT_IRQHandler
+    IRQ BOD_IRQ_IRQHandler
+    IRQ FLASH_IRQ_IRQHandler
+    IRQ USBWAKEUP_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc13xx.s

@@ -0,0 +1,182 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC13xx_svd_v1.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC13xx
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long PIO0_0_IRQHandler
+    .long PIO0_1_IRQHandler
+    .long PIO0_2_IRQHandler
+    .long PIO0_3_IRQHandler
+    .long PIO0_4_IRQHandler
+    .long PIO0_5_IRQHandler
+    .long PIO0_6_IRQHandler
+    .long PIO0_7_IRQHandler
+    .long PIO0_8_IRQHandler
+    .long PIO0_9_IRQHandler
+    .long PIO0_10_IRQHandler
+    .long PIO0_11_IRQHandler
+    .long PIO1_0_IRQHandler
+    .long PIO1_1_IRQHandler
+    .long PIO1_2_IRQHandler
+    .long PIO1_3_IRQHandler
+    .long PIO1_4_IRQHandler
+    .long PIO1_5_IRQHandler
+    .long PIO1_6_IRQHandler
+    .long PIO1_7_IRQHandler
+    .long PIO1_8_IRQHandler
+    .long PIO1_9_IRQHandler
+    .long PIO1_10_IRQHandler
+    .long PIO1_11_IRQHandler
+    .long PIO2_0_IRQHandler
+    .long PIO2_1_IRQHandler
+    .long PIO2_2_IRQHandler
+    .long PIO2_3_IRQHandler
+    .long PIO2_4_IRQHandler
+    .long PIO2_5_IRQHandler
+    .long PIO2_6_IRQHandler
+    .long PIO2_7_IRQHandler
+    .long PIO2_8_IRQHandler
+    .long PIO2_9_IRQHandler
+    .long PIO2_10_IRQHandler
+    .long PIO2_11_IRQHandler
+    .long PIO3_0_IRQHandler
+    .long PIO3_1_IRQHandler
+    .long PIO3_2_IRQHandler
+    .long PIO3_3_IRQHandler
+    .long I2C0_IRQHandler
+    .long CT16B0_IRQHandler
+    .long CT16B1_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long SSP0_IRQHandler
+    .long UART_IRQHandler
+    .long USBIRQ_IRQHandler
+    .long USBFIQ_IRQHandler
+    .long ADC_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long 0
+    .long PIO_3_IRQHandler
+    .long PIO_2_IRQHandler
+    .long PIO_1_IRQHandler
+    .long PIO_0_IRQHandler
+    .long SSP1_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ PIO0_0_IRQHandler
+    IRQ PIO0_1_IRQHandler
+    IRQ PIO0_2_IRQHandler
+    IRQ PIO0_3_IRQHandler
+    IRQ PIO0_4_IRQHandler
+    IRQ PIO0_5_IRQHandler
+    IRQ PIO0_6_IRQHandler
+    IRQ PIO0_7_IRQHandler
+    IRQ PIO0_8_IRQHandler
+    IRQ PIO0_9_IRQHandler
+    IRQ PIO0_10_IRQHandler
+    IRQ PIO0_11_IRQHandler
+    IRQ PIO1_0_IRQHandler
+    IRQ PIO1_1_IRQHandler
+    IRQ PIO1_2_IRQHandler
+    IRQ PIO1_3_IRQHandler
+    IRQ PIO1_4_IRQHandler
+    IRQ PIO1_5_IRQHandler
+    IRQ PIO1_6_IRQHandler
+    IRQ PIO1_7_IRQHandler
+    IRQ PIO1_8_IRQHandler
+    IRQ PIO1_9_IRQHandler
+    IRQ PIO1_10_IRQHandler
+    IRQ PIO1_11_IRQHandler
+    IRQ PIO2_0_IRQHandler
+    IRQ PIO2_1_IRQHandler
+    IRQ PIO2_2_IRQHandler
+    IRQ PIO2_3_IRQHandler
+    IRQ PIO2_4_IRQHandler
+    IRQ PIO2_5_IRQHandler
+    IRQ PIO2_6_IRQHandler
+    IRQ PIO2_7_IRQHandler
+    IRQ PIO2_8_IRQHandler
+    IRQ PIO2_9_IRQHandler
+    IRQ PIO2_10_IRQHandler
+    IRQ PIO2_11_IRQHandler
+    IRQ PIO3_0_IRQHandler
+    IRQ PIO3_1_IRQHandler
+    IRQ PIO3_2_IRQHandler
+    IRQ PIO3_3_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ CT16B0_IRQHandler
+    IRQ CT16B1_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ UART_IRQHandler
+    IRQ USBIRQ_IRQHandler
+    IRQ USBFIQ_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ PIO_3_IRQHandler
+    IRQ PIO_2_IRQHandler
+    IRQ PIO_1_IRQHandler
+    IRQ PIO_0_IRQHandler
+    IRQ SSP1_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc15xx.s

@@ -0,0 +1,161 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC15xx_v0.7.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC15xx Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long WDT_IRQHandler
+    .long BOD_IRQ_IRQHandler
+    .long FLASH_IRQHandler
+    .long EE_IRQHandler
+    .long DMA_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long RIT_IRQHandler
+    .long SCT0_IRQHandler
+    .long SCT1_IRQHandler
+    .long SCT2_IRQHandler
+    .long SCT3_IRQHandler
+    .long MRT_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long I2C0_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long C_CAN0_IRQHandler
+    .long USB_IRQ_IRQHandler
+    .long USB_FIQ_IRQHandler
+    .long USBWAKEUP_IRQHandler
+    .long ADC0_SEQA_IRQHandler
+    .long ADC0_SEQB_IRQHandler
+    .long ADC0_THCMP_IRQHandler
+    .long ADC0_OVR_IRQHandler
+    .long ADC1_SEQA_IRQHandler
+    .long ADC1_SEQB_IRQHandler
+    .long ADC1_THCMP_IRQHandler
+    .long ADC1_OVR_IRQHandler
+    .long DAC_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+    .long CMP2_IRQHandler
+    .long CMP3_IRQHandler
+    .long QEI_IRQHandler
+    .long RTC_ALARM_IRQHandler
+    .long RTC_WAKE_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQ_IRQHandler
+    IRQ FLASH_IRQHandler
+    IRQ EE_IRQHandler
+    IRQ DMA_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ RIT_IRQHandler
+    IRQ SCT0_IRQHandler
+    IRQ SCT1_IRQHandler
+    IRQ SCT2_IRQHandler
+    IRQ SCT3_IRQHandler
+    IRQ MRT_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ C_CAN0_IRQHandler
+    IRQ USB_IRQ_IRQHandler
+    IRQ USB_FIQ_IRQHandler
+    IRQ USBWAKEUP_IRQHandler
+    IRQ ADC0_SEQA_IRQHandler
+    IRQ ADC0_SEQB_IRQHandler
+    IRQ ADC0_THCMP_IRQHandler
+    IRQ ADC0_OVR_IRQHandler
+    IRQ ADC1_SEQA_IRQHandler
+    IRQ ADC1_SEQB_IRQHandler
+    IRQ ADC1_THCMP_IRQHandler
+    IRQ ADC1_OVR_IRQHandler
+    IRQ DAC_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+    IRQ CMP2_IRQHandler
+    IRQ CMP3_IRQHandler
+    IRQ QEI_IRQHandler
+    IRQ RTC_ALARM_IRQHandler
+    IRQ RTC_WAKE_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc176x5x.s

@@ -0,0 +1,137 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC176x5x_v0.2.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC176x/LPC175x M3
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long WDT_IRQHandler
+    .long TIMER0_IRQHandler
+    .long TIMER1_IRQHandler
+    .long TIMER2_IRQHandler
+    .long TIMER3_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long UART3_IRQHandler
+    .long PWM1_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long I2C2_IRQHandler
+    .long SPI_IRQHandler
+    .long SSP0_IRQHandler
+    .long SSP1_IRQHandler
+    .long PLL0_IRQHandler
+    .long RTC_IRQHandler
+    .long EINT0_IRQHandler
+    .long EINT1_IRQHandler
+    .long EINT2_IRQHandler
+    .long EINT3_IRQHandler
+    .long ADC_IRQHandler
+    .long BOD_IRQHandler
+    .long USB_IRQHandler
+    .long CAN_IRQHandler
+    .long DMA_IRQHandler
+    .long I2S_IRQHandler
+    .long ENET_IRQHandler
+    .long RIT_IRQHandler
+    .long MCPWM_IRQHandler
+    .long QEI_IRQHandler
+    .long PLL1_IRQHandler
+    .long USBActivity_IRQHandler
+    .long CANActivity_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ WDT_IRQHandler
+    IRQ TIMER0_IRQHandler
+    IRQ TIMER1_IRQHandler
+    IRQ TIMER2_IRQHandler
+    IRQ TIMER3_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ UART3_IRQHandler
+    IRQ PWM1_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ SPI_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ PLL0_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ EINT0_IRQHandler
+    IRQ EINT1_IRQHandler
+    IRQ EINT2_IRQHandler
+    IRQ EINT3_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ USB_IRQHandler
+    IRQ CAN_IRQHandler
+    IRQ DMA_IRQHandler
+    IRQ I2S_IRQHandler
+    IRQ ENET_IRQHandler
+    IRQ RIT_IRQHandler
+    IRQ MCPWM_IRQHandler
+    IRQ QEI_IRQHandler
+    IRQ PLL1_IRQHandler
+    IRQ USBActivity_IRQHandler
+    IRQ CANActivity_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc18xx.s

@@ -0,0 +1,165 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC18xx.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// Register cmsis file for LPC18xx parts
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DAC_IRQHandler
+    .long 0
+    .long DMA_IRQHandler
+    .long 0
+    .long FLASH_IRQHandler
+    .long ETHERNET_IRQHandler
+    .long SDIO_IRQHandler
+    .long LCD_IRQHandler
+    .long USB0_IRQHandler
+    .long USB1_IRQHandler
+    .long SCT_IRQHandler
+    .long RITIMER_IRQHandler
+    .long TIMER0_IRQHandler
+    .long TIMER1_IRQHandler
+    .long TIMER2_IRQHandler
+    .long TIMER3_IRQHandler
+    .long MCPWM_IRQHandler
+    .long ADC0_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long 0
+    .long ADC1_IRQHandler
+    .long SSP0_IRQHandler
+    .long SSP1_IRQHandler
+    .long USART0_IRQHandler
+    .long UART1_IRQHandler
+    .long USART2_IRQHandler
+    .long USART3_IRQHandler
+    .long I2S0_IRQHandler
+    .long I2S1_IRQHandler
+    .long SPIFI_IRQHandler
+    .long 0
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long EVENTROUTER_IRQHandler
+    .long C_CAN1_IRQHandler
+    .long 0
+    .long 0
+    .long ATIMER_IRQHandler
+    .long RTC_IRQHandler
+    .long 0
+    .long WWDT_IRQHandler
+    .long 0
+    .long C_CAN0_IRQHandler
+    .long QEI_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DAC_IRQHandler
+    IRQ DMA_IRQHandler
+    IRQ FLASH_IRQHandler
+    IRQ ETHERNET_IRQHandler
+    IRQ SDIO_IRQHandler
+    IRQ LCD_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ USB1_IRQHandler
+    IRQ SCT_IRQHandler
+    IRQ RITIMER_IRQHandler
+    IRQ TIMER0_IRQHandler
+    IRQ TIMER1_IRQHandler
+    IRQ TIMER2_IRQHandler
+    IRQ TIMER3_IRQHandler
+    IRQ MCPWM_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ USART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ USART2_IRQHandler
+    IRQ USART3_IRQHandler
+    IRQ I2S0_IRQHandler
+    IRQ I2S1_IRQHandler
+    IRQ SPIFI_IRQHandler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ EVENTROUTER_IRQHandler
+    IRQ C_CAN1_IRQHandler
+    IRQ ATIMER_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ WWDT_IRQHandler
+    IRQ C_CAN0_IRQHandler
+    IRQ QEI_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc408x_7x.s

@@ -0,0 +1,149 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC408x_7x_v0.7.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC408x/7x M4
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long WWDT_IRQHandler
+    .long TIMER0_IRQHandler
+    .long TIMER1_IRQHandler
+    .long TIMER2_IRQHandler
+    .long TIMER3_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long UART3_IRQHandler
+    .long PWM1_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long I2C2_IRQHandler
+    .long 0
+    .long SSP0_IRQHandler
+    .long SSP1_IRQHandler
+    .long 0
+    .long RTC_IRQHandler
+    .long EINT0_IRQHandler
+    .long EINT1_IRQHandler
+    .long EINT2_IRQHandler
+    .long EINT3_IRQHandler
+    .long ADC_IRQHandler
+    .long BOD_IRQHandler
+    .long USB_IRQHandler
+    .long CAN_IRQHandler
+    .long GPDMA_IRQHandler
+    .long I2S_IRQHandler
+    .long ETHERNET_IRQHandler
+    .long SDMMC_IRQHandler
+    .long MCPWM_IRQHandler
+    .long QEI_IRQHandler
+    .long 0
+    .long USB_NEED_CLK_IRQHandler
+    .long 0
+    .long UART4_IRQHandler
+    .long SSP2_IRQHandler
+    .long LCD_IRQHandler
+    .long GPIOINT_IRQHandler
+    .long PWM0_IRQHandler
+    .long EEPROM_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ WWDT_IRQHandler
+    IRQ TIMER0_IRQHandler
+    IRQ TIMER1_IRQHandler
+    IRQ TIMER2_IRQHandler
+    IRQ TIMER3_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ UART3_IRQHandler
+    IRQ PWM1_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ EINT0_IRQHandler
+    IRQ EINT1_IRQHandler
+    IRQ EINT2_IRQHandler
+    IRQ EINT3_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ USB_IRQHandler
+    IRQ CAN_IRQHandler
+    IRQ GPDMA_IRQHandler
+    IRQ I2S_IRQHandler
+    IRQ ETHERNET_IRQHandler
+    IRQ SDMMC_IRQHandler
+    IRQ MCPWM_IRQHandler
+    IRQ QEI_IRQHandler
+    IRQ USB_NEED_CLK_IRQHandler
+    IRQ UART4_IRQHandler
+    IRQ SSP2_IRQHandler
+    IRQ LCD_IRQHandler
+    IRQ GPIOINT_IRQHandler
+    IRQ PWM0_IRQHandler
+    IRQ EEPROM_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc43xx.s

@@ -0,0 +1,168 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC43xx_43Sxx.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// Register cmsis file for LPC43xx parts
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DAC_IRQHandler
+    .long 0
+    .long DMA_IRQHandler
+    .long 0
+    .long FLASH_IRQHandler
+    .long ETHERNET_IRQHandler
+    .long SDIO_IRQHandler
+    .long LCD_IRQHandler
+    .long USB0_IRQHandler
+    .long USB1_IRQHandler
+    .long SCT_IRQHandler
+    .long RITIMER_IRQHandler
+    .long TIMER0_IRQHandler
+    .long TIMER1_IRQHandler
+    .long TIMER2_IRQHandler
+    .long TIMER3_IRQHandler
+    .long MCPWM_IRQHandler
+    .long ADC0_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI_INT_IRQHandler
+    .long ADC1_IRQHandler
+    .long SSP0_IRQHandler
+    .long SSP1_IRQHandler
+    .long USART0_IRQHandler
+    .long UART1_IRQHandler
+    .long USART2_IRQHandler
+    .long USART3_IRQHandler
+    .long I2S0_IRQHandler
+    .long I2S1_IRQHandler
+    .long SPIFI_IRQHandler
+    .long SGPIO_IINT_IRQHandler
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long GINT0_IRQHandler
+    .long GINT1_IRQHandler
+    .long EVENTROUTER_IRQHandler
+    .long C_CAN1_IRQHandler
+    .long 0
+    .long ADCHS_IRQHandler
+    .long ATIMER_IRQHandler
+    .long RTC_IRQHandler
+    .long 0
+    .long WWDT_IRQHandler
+    .long 0
+    .long C_CAN0_IRQHandler
+    .long QEI_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DAC_IRQHandler
+    IRQ DMA_IRQHandler
+    IRQ FLASH_IRQHandler
+    IRQ ETHERNET_IRQHandler
+    IRQ SDIO_IRQHandler
+    IRQ LCD_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ USB1_IRQHandler
+    IRQ SCT_IRQHandler
+    IRQ RITIMER_IRQHandler
+    IRQ TIMER0_IRQHandler
+    IRQ TIMER1_IRQHandler
+    IRQ TIMER2_IRQHandler
+    IRQ TIMER3_IRQHandler
+    IRQ MCPWM_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI_INT_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ USART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ USART2_IRQHandler
+    IRQ USART3_IRQHandler
+    IRQ I2S0_IRQHandler
+    IRQ I2S1_IRQHandler
+    IRQ SPIFI_IRQHandler
+    IRQ SGPIO_IINT_IRQHandler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ EVENTROUTER_IRQHandler
+    IRQ C_CAN1_IRQHandler
+    IRQ ADCHS_IRQHandler
+    IRQ ATIMER_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ WWDT_IRQHandler
+    IRQ C_CAN0_IRQHandler
+    IRQ QEI_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc5410x.s

@@ -0,0 +1,144 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC5410x_v0.4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC5410x Cortex-M4 MCU; Cortex-M0+ coprocessor
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long 0
+    .long DMA_IRQHandler
+    .long GINT0_IRQHandler
+    .long PIN_INT0_IRQHandler
+    .long PIN_INT1_IRQHandler
+    .long PIN_INT2_IRQHandler
+    .long PIN_INT3_IRQHandler
+    .long UTICK_IRQHandler
+    .long MRT_IRQHandler
+    .long CT32B0_IRQHandler
+    .long CT32B1_IRQHandler
+    .long CT32B2_IRQHandler
+    .long CT32B3_IRQHandler
+    .long CT32B4_IRQHandler
+    .long SCT0_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long UART3_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long I2C2_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long ADC_SEQA_IRQHandler
+    .long ADC_SEQB_IRQHandler
+    .long ADC_THCMP_IRQHandler
+    .long RTC_IRQHandler
+    .long 0
+    .long MAILBOX_IRQHandler
+    .long GINT1_IRQHandler
+    .long PIN_INT4_IRQHandler
+    .long PIN_INT5_IRQHandler
+    .long PIN_INT6_IRQHandler
+    .long PIN_INT7_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long RIT_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ DMA_IRQHandler
+    IRQ GINT0_IRQHandler
+    IRQ PIN_INT0_IRQHandler
+    IRQ PIN_INT1_IRQHandler
+    IRQ PIN_INT2_IRQHandler
+    IRQ PIN_INT3_IRQHandler
+    IRQ UTICK_IRQHandler
+    IRQ MRT_IRQHandler
+    IRQ CT32B0_IRQHandler
+    IRQ CT32B1_IRQHandler
+    IRQ CT32B2_IRQHandler
+    IRQ CT32B3_IRQHandler
+    IRQ CT32B4_IRQHandler
+    IRQ SCT0_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ UART3_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ ADC_SEQA_IRQHandler
+    IRQ ADC_SEQB_IRQHandler
+    IRQ ADC_THCMP_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ MAILBOX_IRQHandler
+    IRQ GINT1_IRQHandler
+    IRQ PIN_INT4_IRQHandler
+    IRQ PIN_INT5_IRQHandler
+    IRQ PIN_INT6_IRQHandler
+    IRQ PIN_INT7_IRQHandler
+    IRQ RIT_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/lpc800.s

@@ -0,0 +1,120 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC800_v0.3.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// LPC800
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long 0
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long 0
+    .long 0
+    .long I2C_IRQHandler
+    .long SCT_IRQHandler
+    .long MRT_IRQHandler
+    .long CMP_IRQHandler
+    .long WDT_IRQHandler
+    .long BOD_IRQHandler
+    .long FLASH_IRQ_IRQHandler
+    .long WKT_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long PININT0_IRQHandler
+    .long PININT1_IRQHandler
+    .long PININT2_IRQHandler
+    .long PININT3_IRQHandler
+    .long PININT4_IRQHandler
+    .long PININT5_IRQHandler
+    .long PININT6_IRQHandler
+    .long PININT7_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ I2C_IRQHandler
+    IRQ SCT_IRQHandler
+    IRQ MRT_IRQHandler
+    IRQ CMP_IRQHandler
+    IRQ WDT_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ FLASH_IRQ_IRQHandler
+    IRQ WKT_IRQHandler
+    IRQ PININT0_IRQHandler
+    IRQ PININT1_IRQHandler
+    IRQ PININT2_IRQHandler
+    IRQ PININT3_IRQHandler
+    IRQ PININT4_IRQHandler
+    IRQ PININT5_IRQHandler
+    IRQ PININT6_IRQHandler
+    IRQ PININT7_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mimxrt1011.s

@@ -0,0 +1,227 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MIMXRT1011.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MIMXRT1011DAE5A
+*/
+
+//     Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_IRQHandler
+    .long DMA1_IRQHandler
+    .long DMA2_IRQHandler
+    .long DMA3_IRQHandler
+    .long DMA4_IRQHandler
+    .long DMA5_IRQHandler
+    .long DMA6_IRQHandler
+    .long DMA7_IRQHandler
+    .long DMA8_IRQHandler
+    .long DMA9_IRQHandler
+    .long DMA10_IRQHandler
+    .long DMA11_IRQHandler
+    .long DMA12_IRQHandler
+    .long DMA13_IRQHandler
+    .long DMA14_IRQHandler
+    .long DMA15_IRQHandler
+    .long DMA_ERROR_IRQHandler
+    .long CTI0_ERROR_IRQHandler
+    .long CTI1_ERROR_IRQHandler
+    .long CORE_IRQHandler
+    .long LPUART1_IRQHandler
+    .long LPUART2_IRQHandler
+    .long LPUART3_IRQHandler
+    .long LPUART4_IRQHandler
+    .long PIT_IRQHandler
+    .long USB_OTG1_IRQHandler
+    .long FLEXSPI_IRQHandler
+    .long FLEXRAM_IRQHandler
+    .long LPI2C1_IRQHandler
+    .long LPI2C2_IRQHandler
+    .long GPT1_IRQHandler
+    .long GPT2_IRQHandler
+    .long LPSPI1_IRQHandler
+    .long LPSPI2_IRQHandler
+    .long PWM1_0_IRQHandler
+    .long PWM1_1_IRQHandler
+    .long PWM1_2_IRQHandler
+    .long PWM1_3_IRQHandler
+    .long PWM1_FAULT_IRQHandler
+    .long KPP_IRQHandler
+    .long SRC_IRQHandler
+    .long GPR_IRQ_IRQHandler
+    .long CCM_1_IRQHandler
+    .long CCM_2_IRQHandler
+    .long EWM_IRQHandler
+    .long WDOG2_IRQHandler
+    .long SNVS_HP_WRAPPER_IRQHandler
+    .long SNVS_HP_WRAPPER_TZ_IRQHandler
+    .long SNVS_LP_WRAPPER_IRQHandler
+    .long CSU_IRQHandler
+    .long DCP_IRQHandler
+    .long DCP_VMI_IRQHandler
+    .long Reserved68_IRQHandler
+    .long TRNG_IRQHandler
+    .long Reserved70_IRQHandler
+    .long Reserved71_IRQHandler
+    .long SAI1_IRQHandler
+    .long RTWDOG_IRQHandler
+    .long SAI3_RX_IRQHandler
+    .long SAI3_TX_IRQHandler
+    .long SPDIF_IRQHandler
+    .long PMU_IRQHandler
+    .long XBAR1_IRQ_0_1_2_3_IRQHandler
+    .long TEMP_LOW_HIGH_IRQHandler
+    .long TEMP_PANIC_IRQHandler
+    .long USB_PHY_IRQHandler
+    .long GPC_IRQHandler
+    .long ADC1_IRQHandler
+    .long FLEXIO1_IRQHandler
+    .long DCDC_IRQHandler
+    .long GPIO1_Combined_0_15_IRQHandler
+    .long GPIO1_Combined_16_31_IRQHandler
+    .long GPIO2_Combined_0_15_IRQHandler
+    .long GPIO5_Combined_0_15_IRQHandler
+    .long WDOG1_IRQHandler
+    .long ADC_ETC_IRQ0_IRQHandler
+    .long ADC_ETC_IRQ1_IRQHandler
+    .long ADC_ETC_IRQ2_IRQHandler
+    .long ADC_ETC_IRQ3_IRQHandler
+    .long ADC_ETC_ERROR_IRQ_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_IRQHandler
+    IRQ DMA1_IRQHandler
+    IRQ DMA2_IRQHandler
+    IRQ DMA3_IRQHandler
+    IRQ DMA4_IRQHandler
+    IRQ DMA5_IRQHandler
+    IRQ DMA6_IRQHandler
+    IRQ DMA7_IRQHandler
+    IRQ DMA8_IRQHandler
+    IRQ DMA9_IRQHandler
+    IRQ DMA10_IRQHandler
+    IRQ DMA11_IRQHandler
+    IRQ DMA12_IRQHandler
+    IRQ DMA13_IRQHandler
+    IRQ DMA14_IRQHandler
+    IRQ DMA15_IRQHandler
+    IRQ DMA_ERROR_IRQHandler
+    IRQ CTI0_ERROR_IRQHandler
+    IRQ CTI1_ERROR_IRQHandler
+    IRQ CORE_IRQHandler
+    IRQ LPUART1_IRQHandler
+    IRQ LPUART2_IRQHandler
+    IRQ LPUART3_IRQHandler
+    IRQ LPUART4_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ USB_OTG1_IRQHandler
+    IRQ FLEXSPI_IRQHandler
+    IRQ FLEXRAM_IRQHandler
+    IRQ LPI2C1_IRQHandler
+    IRQ LPI2C2_IRQHandler
+    IRQ GPT1_IRQHandler
+    IRQ GPT2_IRQHandler
+    IRQ LPSPI1_IRQHandler
+    IRQ LPSPI2_IRQHandler
+    IRQ PWM1_0_IRQHandler
+    IRQ PWM1_1_IRQHandler
+    IRQ PWM1_2_IRQHandler
+    IRQ PWM1_3_IRQHandler
+    IRQ PWM1_FAULT_IRQHandler
+    IRQ KPP_IRQHandler
+    IRQ SRC_IRQHandler
+    IRQ GPR_IRQ_IRQHandler
+    IRQ CCM_1_IRQHandler
+    IRQ CCM_2_IRQHandler
+    IRQ EWM_IRQHandler
+    IRQ WDOG2_IRQHandler
+    IRQ SNVS_HP_WRAPPER_IRQHandler
+    IRQ SNVS_HP_WRAPPER_TZ_IRQHandler
+    IRQ SNVS_LP_WRAPPER_IRQHandler
+    IRQ CSU_IRQHandler
+    IRQ DCP_IRQHandler
+    IRQ DCP_VMI_IRQHandler
+    IRQ Reserved68_IRQHandler
+    IRQ TRNG_IRQHandler
+    IRQ Reserved70_IRQHandler
+    IRQ Reserved71_IRQHandler
+    IRQ SAI1_IRQHandler
+    IRQ RTWDOG_IRQHandler
+    IRQ SAI3_RX_IRQHandler
+    IRQ SAI3_TX_IRQHandler
+    IRQ SPDIF_IRQHandler
+    IRQ PMU_IRQHandler
+    IRQ XBAR1_IRQ_0_1_2_3_IRQHandler
+    IRQ TEMP_LOW_HIGH_IRQHandler
+    IRQ TEMP_PANIC_IRQHandler
+    IRQ USB_PHY_IRQHandler
+    IRQ GPC_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ FLEXIO1_IRQHandler
+    IRQ DCDC_IRQHandler
+    IRQ GPIO1_Combined_0_15_IRQHandler
+    IRQ GPIO1_Combined_16_31_IRQHandler
+    IRQ GPIO2_Combined_0_15_IRQHandler
+    IRQ GPIO5_Combined_0_15_IRQHandler
+    IRQ WDOG1_IRQHandler
+    IRQ ADC_ETC_IRQ0_IRQHandler
+    IRQ ADC_ETC_IRQ1_IRQHandler
+    IRQ ADC_ETC_IRQ2_IRQHandler
+    IRQ ADC_ETC_IRQ3_IRQHandler
+    IRQ ADC_ETC_ERROR_IRQ_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mimxrt1021.s

@@ -0,0 +1,350 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MIMXRT1021.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MIMXRT1021DAG5A
+*/
+
+//     Copyright 2016-2020 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_DMA16_IRQHandler
+    .long DMA1_DMA17_IRQHandler
+    .long DMA2_DMA18_IRQHandler
+    .long DMA3_DMA19_IRQHandler
+    .long DMA4_DMA20_IRQHandler
+    .long DMA5_DMA21_IRQHandler
+    .long DMA6_DMA22_IRQHandler
+    .long DMA7_DMA23_IRQHandler
+    .long DMA8_DMA24_IRQHandler
+    .long DMA9_DMA25_IRQHandler
+    .long DMA10_DMA26_IRQHandler
+    .long DMA11_DMA27_IRQHandler
+    .long DMA12_DMA28_IRQHandler
+    .long DMA13_DMA29_IRQHandler
+    .long DMA14_DMA30_IRQHandler
+    .long DMA15_DMA31_IRQHandler
+    .long DMA_ERROR_IRQHandler
+    .long CTI0_ERROR_IRQHandler
+    .long CTI1_ERROR_IRQHandler
+    .long CORE_IRQHandler
+    .long LPUART1_IRQHandler
+    .long LPUART2_IRQHandler
+    .long LPUART3_IRQHandler
+    .long LPUART4_IRQHandler
+    .long LPUART5_IRQHandler
+    .long LPUART6_IRQHandler
+    .long LPUART7_IRQHandler
+    .long LPUART8_IRQHandler
+    .long LPI2C1_IRQHandler
+    .long LPI2C2_IRQHandler
+    .long LPI2C3_IRQHandler
+    .long LPI2C4_IRQHandler
+    .long LPSPI1_IRQHandler
+    .long LPSPI2_IRQHandler
+    .long LPSPI3_IRQHandler
+    .long LPSPI4_IRQHandler
+    .long CAN1_IRQHandler
+    .long CAN2_IRQHandler
+    .long FLEXRAM_IRQHandler
+    .long KPP_IRQHandler
+    .long Reserved56_IRQHandler
+    .long GPR_IRQ_IRQHandler
+    .long Reserved58_IRQHandler
+    .long Reserved59_IRQHandler
+    .long Reserved60_IRQHandler
+    .long WDOG2_IRQHandler
+    .long SNVS_HP_WRAPPER_IRQHandler
+    .long SNVS_HP_WRAPPER_TZ_IRQHandler
+    .long SNVS_LP_HP_WRAPPER_IRQHandler
+    .long CSU_IRQHandler
+    .long DCP_IRQHandler
+    .long DCP_VMI_IRQHandler
+    .long Reserved68_IRQHandler
+    .long TRNG_IRQHandler
+    .long 0
+    .long BEE_IRQHandler
+    .long SAI1_IRQHandler
+    .long SAI2_IRQHandler
+    .long SAI3_RX_IRQHandler
+    .long SAI3_TX_IRQHandler
+    .long SPDIF_IRQHandler
+    .long PMU_IRQHandler
+    .long Reserved78_IRQHandler
+    .long TEMP_LOW_HIGH_IRQHandler
+    .long TEMP_PANIC_IRQHandler
+    .long USB_PHY_IRQHandler
+    .long Reserved82_IRQHandler
+    .long ADC1_IRQHandler
+    .long ADC2_IRQHandler
+    .long DCDC_IRQHandler
+    .long Reserved86_IRQHandler
+    .long Reserved87_IRQHandler
+    .long GPIO1_INT0_IRQHandler
+    .long GPIO1_INT1_IRQHandler
+    .long GPIO1_INT2_IRQHandler
+    .long GPIO1_INT3_IRQHandler
+    .long GPIO1_INT4_IRQHandler
+    .long GPIO1_INT5_IRQHandler
+    .long GPIO1_INT6_IRQHandler
+    .long GPIO1_INT7_IRQHandler
+    .long GPIO1_Combined_0_15_IRQHandler
+    .long GPIO1_Combined_16_31_IRQHandler
+    .long GPIO2_Combined_0_15_IRQHandler
+    .long GPIO2_Combined_16_31_IRQHandler
+    .long GPIO3_Combined_0_15_IRQHandler
+    .long GPIO3_Combined_16_31_IRQHandler
+    .long Reserved102_IRQHandler
+    .long Reserved103_IRQHandler
+    .long GPIO5_Combined_0_15_IRQHandler
+    .long GPIO5_Combined_16_31_IRQHandler
+    .long FLEXIO1_IRQHandler
+    .long Reserved107_IRQHandler
+    .long WDOG1_IRQHandler
+    .long RTWDOG_IRQHandler
+    .long EWM_IRQHandler
+    .long CCM_1_IRQHandler
+    .long CCM_2_IRQHandler
+    .long GPC_IRQHandler
+    .long SRC_IRQHandler
+    .long Reserved115_IRQHandler
+    .long GPT1_IRQHandler
+    .long GPT2_IRQHandler
+    .long PWM1_0_IRQHandler
+    .long PWM1_1_IRQHandler
+    .long PWM1_2_IRQHandler
+    .long PWM1_3_IRQHandler
+    .long PWM1_FAULT_IRQHandler
+    .long Reserved123_IRQHandler
+    .long FLEXSPI_IRQHandler
+    .long SEMC_IRQHandler
+    .long USDHC1_IRQHandler
+    .long USDHC2_IRQHandler
+    .long Reserved128_IRQHandler
+    .long USB_OTG1_IRQHandler
+    .long ENET_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long XBAR1_IRQ_0_1_IRQHandler
+    .long XBAR1_IRQ_2_3_IRQHandler
+    .long ADC_ETC_IRQ0_IRQHandler
+    .long ADC_ETC_IRQ1_IRQHandler
+    .long ADC_ETC_IRQ2_IRQHandler
+    .long ADC_ETC_ERROR_IRQ_IRQHandler
+    .long PIT_IRQHandler
+    .long ACMP1_IRQHandler
+    .long ACMP2_IRQHandler
+    .long ACMP3_IRQHandler
+    .long ACMP4_IRQHandler
+    .long Reserved143_IRQHandler
+    .long Reserved144_IRQHandler
+    .long ENC1_IRQHandler
+    .long ENC2_IRQHandler
+    .long Reserved147_IRQHandler
+    .long Reserved148_IRQHandler
+    .long TMR1_IRQHandler
+    .long TMR2_IRQHandler
+    .long Reserved151_IRQHandler
+    .long Reserved152_IRQHandler
+    .long PWM2_0_IRQHandler
+    .long PWM2_1_IRQHandler
+    .long PWM2_2_IRQHandler
+    .long PWM2_3_IRQHandler
+    .long PWM2_FAULT_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_DMA16_IRQHandler
+    IRQ DMA1_DMA17_IRQHandler
+    IRQ DMA2_DMA18_IRQHandler
+    IRQ DMA3_DMA19_IRQHandler
+    IRQ DMA4_DMA20_IRQHandler
+    IRQ DMA5_DMA21_IRQHandler
+    IRQ DMA6_DMA22_IRQHandler
+    IRQ DMA7_DMA23_IRQHandler
+    IRQ DMA8_DMA24_IRQHandler
+    IRQ DMA9_DMA25_IRQHandler
+    IRQ DMA10_DMA26_IRQHandler
+    IRQ DMA11_DMA27_IRQHandler
+    IRQ DMA12_DMA28_IRQHandler
+    IRQ DMA13_DMA29_IRQHandler
+    IRQ DMA14_DMA30_IRQHandler
+    IRQ DMA15_DMA31_IRQHandler
+    IRQ DMA_ERROR_IRQHandler
+    IRQ CTI0_ERROR_IRQHandler
+    IRQ CTI1_ERROR_IRQHandler
+    IRQ CORE_IRQHandler
+    IRQ LPUART1_IRQHandler
+    IRQ LPUART2_IRQHandler
+    IRQ LPUART3_IRQHandler
+    IRQ LPUART4_IRQHandler
+    IRQ LPUART5_IRQHandler
+    IRQ LPUART6_IRQHandler
+    IRQ LPUART7_IRQHandler
+    IRQ LPUART8_IRQHandler
+    IRQ LPI2C1_IRQHandler
+    IRQ LPI2C2_IRQHandler
+    IRQ LPI2C3_IRQHandler
+    IRQ LPI2C4_IRQHandler
+    IRQ LPSPI1_IRQHandler
+    IRQ LPSPI2_IRQHandler
+    IRQ LPSPI3_IRQHandler
+    IRQ LPSPI4_IRQHandler
+    IRQ CAN1_IRQHandler
+    IRQ CAN2_IRQHandler
+    IRQ FLEXRAM_IRQHandler
+    IRQ KPP_IRQHandler
+    IRQ Reserved56_IRQHandler
+    IRQ GPR_IRQ_IRQHandler
+    IRQ Reserved58_IRQHandler
+    IRQ Reserved59_IRQHandler
+    IRQ Reserved60_IRQHandler
+    IRQ WDOG2_IRQHandler
+    IRQ SNVS_HP_WRAPPER_IRQHandler
+    IRQ SNVS_HP_WRAPPER_TZ_IRQHandler
+    IRQ SNVS_LP_HP_WRAPPER_IRQHandler
+    IRQ CSU_IRQHandler
+    IRQ DCP_IRQHandler
+    IRQ DCP_VMI_IRQHandler
+    IRQ Reserved68_IRQHandler
+    IRQ TRNG_IRQHandler
+    IRQ BEE_IRQHandler
+    IRQ SAI1_IRQHandler
+    IRQ SAI2_IRQHandler
+    IRQ SAI3_RX_IRQHandler
+    IRQ SAI3_TX_IRQHandler
+    IRQ SPDIF_IRQHandler
+    IRQ PMU_IRQHandler
+    IRQ Reserved78_IRQHandler
+    IRQ TEMP_LOW_HIGH_IRQHandler
+    IRQ TEMP_PANIC_IRQHandler
+    IRQ USB_PHY_IRQHandler
+    IRQ Reserved82_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ ADC2_IRQHandler
+    IRQ DCDC_IRQHandler
+    IRQ Reserved86_IRQHandler
+    IRQ Reserved87_IRQHandler
+    IRQ GPIO1_INT0_IRQHandler
+    IRQ GPIO1_INT1_IRQHandler
+    IRQ GPIO1_INT2_IRQHandler
+    IRQ GPIO1_INT3_IRQHandler
+    IRQ GPIO1_INT4_IRQHandler
+    IRQ GPIO1_INT5_IRQHandler
+    IRQ GPIO1_INT6_IRQHandler
+    IRQ GPIO1_INT7_IRQHandler
+    IRQ GPIO1_Combined_0_15_IRQHandler
+    IRQ GPIO1_Combined_16_31_IRQHandler
+    IRQ GPIO2_Combined_0_15_IRQHandler
+    IRQ GPIO2_Combined_16_31_IRQHandler
+    IRQ GPIO3_Combined_0_15_IRQHandler
+    IRQ GPIO3_Combined_16_31_IRQHandler
+    IRQ Reserved102_IRQHandler
+    IRQ Reserved103_IRQHandler
+    IRQ GPIO5_Combined_0_15_IRQHandler
+    IRQ GPIO5_Combined_16_31_IRQHandler
+    IRQ FLEXIO1_IRQHandler
+    IRQ Reserved107_IRQHandler
+    IRQ WDOG1_IRQHandler
+    IRQ RTWDOG_IRQHandler
+    IRQ EWM_IRQHandler
+    IRQ CCM_1_IRQHandler
+    IRQ CCM_2_IRQHandler
+    IRQ GPC_IRQHandler
+    IRQ SRC_IRQHandler
+    IRQ Reserved115_IRQHandler
+    IRQ GPT1_IRQHandler
+    IRQ GPT2_IRQHandler
+    IRQ PWM1_0_IRQHandler
+    IRQ PWM1_1_IRQHandler
+    IRQ PWM1_2_IRQHandler
+    IRQ PWM1_3_IRQHandler
+    IRQ PWM1_FAULT_IRQHandler
+    IRQ Reserved123_IRQHandler
+    IRQ FLEXSPI_IRQHandler
+    IRQ SEMC_IRQHandler
+    IRQ USDHC1_IRQHandler
+    IRQ USDHC2_IRQHandler
+    IRQ Reserved128_IRQHandler
+    IRQ USB_OTG1_IRQHandler
+    IRQ ENET_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ XBAR1_IRQ_0_1_IRQHandler
+    IRQ XBAR1_IRQ_2_3_IRQHandler
+    IRQ ADC_ETC_IRQ0_IRQHandler
+    IRQ ADC_ETC_IRQ1_IRQHandler
+    IRQ ADC_ETC_IRQ2_IRQHandler
+    IRQ ADC_ETC_ERROR_IRQ_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ ACMP1_IRQHandler
+    IRQ ACMP2_IRQHandler
+    IRQ ACMP3_IRQHandler
+    IRQ ACMP4_IRQHandler
+    IRQ Reserved143_IRQHandler
+    IRQ Reserved144_IRQHandler
+    IRQ ENC1_IRQHandler
+    IRQ ENC2_IRQHandler
+    IRQ Reserved147_IRQHandler
+    IRQ Reserved148_IRQHandler
+    IRQ TMR1_IRQHandler
+    IRQ TMR2_IRQHandler
+    IRQ Reserved151_IRQHandler
+    IRQ Reserved152_IRQHandler
+    IRQ PWM2_0_IRQHandler
+    IRQ PWM2_1_IRQHandler
+    IRQ PWM2_2_IRQHandler
+    IRQ PWM2_3_IRQHandler
+    IRQ PWM2_FAULT_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mimxrt1052.s

@@ -0,0 +1,371 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MIMXRT1052.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MIMXRT1052DVL6B
+*/
+
+//     Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_DMA16_IRQHandler
+    .long DMA1_DMA17_IRQHandler
+    .long DMA2_DMA18_IRQHandler
+    .long DMA3_DMA19_IRQHandler
+    .long DMA4_DMA20_IRQHandler
+    .long DMA5_DMA21_IRQHandler
+    .long DMA6_DMA22_IRQHandler
+    .long DMA7_DMA23_IRQHandler
+    .long DMA8_DMA24_IRQHandler
+    .long DMA9_DMA25_IRQHandler
+    .long DMA10_DMA26_IRQHandler
+    .long DMA11_DMA27_IRQHandler
+    .long DMA12_DMA28_IRQHandler
+    .long DMA13_DMA29_IRQHandler
+    .long DMA14_DMA30_IRQHandler
+    .long DMA15_DMA31_IRQHandler
+    .long DMA_ERROR_IRQHandler
+    .long CTI0_ERROR_IRQHandler
+    .long CTI1_ERROR_IRQHandler
+    .long CORE_IRQHandler
+    .long LPUART1_IRQHandler
+    .long LPUART2_IRQHandler
+    .long LPUART3_IRQHandler
+    .long LPUART4_IRQHandler
+    .long LPUART5_IRQHandler
+    .long LPUART6_IRQHandler
+    .long LPUART7_IRQHandler
+    .long LPUART8_IRQHandler
+    .long LPI2C1_IRQHandler
+    .long LPI2C2_IRQHandler
+    .long LPI2C3_IRQHandler
+    .long LPI2C4_IRQHandler
+    .long LPSPI1_IRQHandler
+    .long LPSPI2_IRQHandler
+    .long LPSPI3_IRQHandler
+    .long LPSPI4_IRQHandler
+    .long CAN1_IRQHandler
+    .long CAN2_IRQHandler
+    .long FLEXRAM_IRQHandler
+    .long KPP_IRQHandler
+    .long TSC_DIG_IRQHandler
+    .long GPR_IRQ_IRQHandler
+    .long LCDIF_IRQHandler
+    .long CSI_IRQHandler
+    .long PXP_IRQHandler
+    .long WDOG2_IRQHandler
+    .long SNVS_HP_WRAPPER_IRQHandler
+    .long SNVS_HP_WRAPPER_TZ_IRQHandler
+    .long SNVS_LP_WRAPPER_IRQHandler
+    .long CSU_IRQHandler
+    .long DCP_IRQHandler
+    .long DCP_VMI_IRQHandler
+    .long Reserved68_IRQHandler
+    .long TRNG_IRQHandler
+    .long SJC_IRQHandler
+    .long BEE_IRQHandler
+    .long SAI1_IRQHandler
+    .long SAI2_IRQHandler
+    .long SAI3_RX_IRQHandler
+    .long SAI3_TX_IRQHandler
+    .long SPDIF_IRQHandler
+    .long PMU_EVENT_IRQHandler
+    .long Reserved78_IRQHandler
+    .long TEMP_LOW_HIGH_IRQHandler
+    .long TEMP_PANIC_IRQHandler
+    .long USB_PHY1_IRQHandler
+    .long USB_PHY2_IRQHandler
+    .long ADC1_IRQHandler
+    .long ADC2_IRQHandler
+    .long DCDC_IRQHandler
+    .long Reserved86_IRQHandler
+    .long Reserved87_IRQHandler
+    .long GPIO1_INT0_IRQHandler
+    .long GPIO1_INT1_IRQHandler
+    .long GPIO1_INT2_IRQHandler
+    .long GPIO1_INT3_IRQHandler
+    .long GPIO1_INT4_IRQHandler
+    .long GPIO1_INT5_IRQHandler
+    .long GPIO1_INT6_IRQHandler
+    .long GPIO1_INT7_IRQHandler
+    .long GPIO1_Combined_0_15_IRQHandler
+    .long GPIO1_Combined_16_31_IRQHandler
+    .long GPIO2_Combined_0_15_IRQHandler
+    .long GPIO2_Combined_16_31_IRQHandler
+    .long GPIO3_Combined_0_15_IRQHandler
+    .long GPIO3_Combined_16_31_IRQHandler
+    .long GPIO4_Combined_0_15_IRQHandler
+    .long GPIO4_Combined_16_31_IRQHandler
+    .long GPIO5_Combined_0_15_IRQHandler
+    .long GPIO5_Combined_16_31_IRQHandler
+    .long FLEXIO1_IRQHandler
+    .long FLEXIO2_IRQHandler
+    .long WDOG1_IRQHandler
+    .long RTWDOG_IRQHandler
+    .long EWM_IRQHandler
+    .long CCM_1_IRQHandler
+    .long CCM_2_IRQHandler
+    .long GPC_IRQHandler
+    .long SRC_IRQHandler
+    .long Reserved115_IRQHandler
+    .long GPT1_IRQHandler
+    .long GPT2_IRQHandler
+    .long PWM1_0_IRQHandler
+    .long PWM1_1_IRQHandler
+    .long PWM1_2_IRQHandler
+    .long PWM1_3_IRQHandler
+    .long PWM1_FAULT_IRQHandler
+    .long Reserved123_IRQHandler
+    .long FLEXSPI_IRQHandler
+    .long SEMC_IRQHandler
+    .long USDHC1_IRQHandler
+    .long USDHC2_IRQHandler
+    .long USB_OTG2_IRQHandler
+    .long USB_OTG1_IRQHandler
+    .long ENET_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long XBAR1_IRQ_0_1_IRQHandler
+    .long XBAR1_IRQ_2_3_IRQHandler
+    .long ADC_ETC_IRQ0_IRQHandler
+    .long ADC_ETC_IRQ1_IRQHandler
+    .long ADC_ETC_IRQ2_IRQHandler
+    .long ADC_ETC_ERROR_IRQ_IRQHandler
+    .long PIT_IRQHandler
+    .long ACMP1_IRQHandler
+    .long ACMP2_IRQHandler
+    .long ACMP3_IRQHandler
+    .long ACMP4_IRQHandler
+    .long Reserved143_IRQHandler
+    .long Reserved144_IRQHandler
+    .long ENC1_IRQHandler
+    .long ENC2_IRQHandler
+    .long ENC3_IRQHandler
+    .long ENC4_IRQHandler
+    .long TMR1_IRQHandler
+    .long TMR2_IRQHandler
+    .long TMR3_IRQHandler
+    .long TMR4_IRQHandler
+    .long PWM2_0_IRQHandler
+    .long PWM2_1_IRQHandler
+    .long PWM2_2_IRQHandler
+    .long PWM2_3_IRQHandler
+    .long PWM2_FAULT_IRQHandler
+    .long PWM3_0_IRQHandler
+    .long PWM3_1_IRQHandler
+    .long PWM3_2_IRQHandler
+    .long PWM3_3_IRQHandler
+    .long PWM3_FAULT_IRQHandler
+    .long PWM4_0_IRQHandler
+    .long PWM4_1_IRQHandler
+    .long PWM4_2_IRQHandler
+    .long PWM4_3_IRQHandler
+    .long PWM4_FAULT_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_DMA16_IRQHandler
+    IRQ DMA1_DMA17_IRQHandler
+    IRQ DMA2_DMA18_IRQHandler
+    IRQ DMA3_DMA19_IRQHandler
+    IRQ DMA4_DMA20_IRQHandler
+    IRQ DMA5_DMA21_IRQHandler
+    IRQ DMA6_DMA22_IRQHandler
+    IRQ DMA7_DMA23_IRQHandler
+    IRQ DMA8_DMA24_IRQHandler
+    IRQ DMA9_DMA25_IRQHandler
+    IRQ DMA10_DMA26_IRQHandler
+    IRQ DMA11_DMA27_IRQHandler
+    IRQ DMA12_DMA28_IRQHandler
+    IRQ DMA13_DMA29_IRQHandler
+    IRQ DMA14_DMA30_IRQHandler
+    IRQ DMA15_DMA31_IRQHandler
+    IRQ DMA_ERROR_IRQHandler
+    IRQ CTI0_ERROR_IRQHandler
+    IRQ CTI1_ERROR_IRQHandler
+    IRQ CORE_IRQHandler
+    IRQ LPUART1_IRQHandler
+    IRQ LPUART2_IRQHandler
+    IRQ LPUART3_IRQHandler
+    IRQ LPUART4_IRQHandler
+    IRQ LPUART5_IRQHandler
+    IRQ LPUART6_IRQHandler
+    IRQ LPUART7_IRQHandler
+    IRQ LPUART8_IRQHandler
+    IRQ LPI2C1_IRQHandler
+    IRQ LPI2C2_IRQHandler
+    IRQ LPI2C3_IRQHandler
+    IRQ LPI2C4_IRQHandler
+    IRQ LPSPI1_IRQHandler
+    IRQ LPSPI2_IRQHandler
+    IRQ LPSPI3_IRQHandler
+    IRQ LPSPI4_IRQHandler
+    IRQ CAN1_IRQHandler
+    IRQ CAN2_IRQHandler
+    IRQ FLEXRAM_IRQHandler
+    IRQ KPP_IRQHandler
+    IRQ TSC_DIG_IRQHandler
+    IRQ GPR_IRQ_IRQHandler
+    IRQ LCDIF_IRQHandler
+    IRQ CSI_IRQHandler
+    IRQ PXP_IRQHandler
+    IRQ WDOG2_IRQHandler
+    IRQ SNVS_HP_WRAPPER_IRQHandler
+    IRQ SNVS_HP_WRAPPER_TZ_IRQHandler
+    IRQ SNVS_LP_WRAPPER_IRQHandler
+    IRQ CSU_IRQHandler
+    IRQ DCP_IRQHandler
+    IRQ DCP_VMI_IRQHandler
+    IRQ Reserved68_IRQHandler
+    IRQ TRNG_IRQHandler
+    IRQ SJC_IRQHandler
+    IRQ BEE_IRQHandler
+    IRQ SAI1_IRQHandler
+    IRQ SAI2_IRQHandler
+    IRQ SAI3_RX_IRQHandler
+    IRQ SAI3_TX_IRQHandler
+    IRQ SPDIF_IRQHandler
+    IRQ PMU_EVENT_IRQHandler
+    IRQ Reserved78_IRQHandler
+    IRQ TEMP_LOW_HIGH_IRQHandler
+    IRQ TEMP_PANIC_IRQHandler
+    IRQ USB_PHY1_IRQHandler
+    IRQ USB_PHY2_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ ADC2_IRQHandler
+    IRQ DCDC_IRQHandler
+    IRQ Reserved86_IRQHandler
+    IRQ Reserved87_IRQHandler
+    IRQ GPIO1_INT0_IRQHandler
+    IRQ GPIO1_INT1_IRQHandler
+    IRQ GPIO1_INT2_IRQHandler
+    IRQ GPIO1_INT3_IRQHandler
+    IRQ GPIO1_INT4_IRQHandler
+    IRQ GPIO1_INT5_IRQHandler
+    IRQ GPIO1_INT6_IRQHandler
+    IRQ GPIO1_INT7_IRQHandler
+    IRQ GPIO1_Combined_0_15_IRQHandler
+    IRQ GPIO1_Combined_16_31_IRQHandler
+    IRQ GPIO2_Combined_0_15_IRQHandler
+    IRQ GPIO2_Combined_16_31_IRQHandler
+    IRQ GPIO3_Combined_0_15_IRQHandler
+    IRQ GPIO3_Combined_16_31_IRQHandler
+    IRQ GPIO4_Combined_0_15_IRQHandler
+    IRQ GPIO4_Combined_16_31_IRQHandler
+    IRQ GPIO5_Combined_0_15_IRQHandler
+    IRQ GPIO5_Combined_16_31_IRQHandler
+    IRQ FLEXIO1_IRQHandler
+    IRQ FLEXIO2_IRQHandler
+    IRQ WDOG1_IRQHandler
+    IRQ RTWDOG_IRQHandler
+    IRQ EWM_IRQHandler
+    IRQ CCM_1_IRQHandler
+    IRQ CCM_2_IRQHandler
+    IRQ GPC_IRQHandler
+    IRQ SRC_IRQHandler
+    IRQ Reserved115_IRQHandler
+    IRQ GPT1_IRQHandler
+    IRQ GPT2_IRQHandler
+    IRQ PWM1_0_IRQHandler
+    IRQ PWM1_1_IRQHandler
+    IRQ PWM1_2_IRQHandler
+    IRQ PWM1_3_IRQHandler
+    IRQ PWM1_FAULT_IRQHandler
+    IRQ Reserved123_IRQHandler
+    IRQ FLEXSPI_IRQHandler
+    IRQ SEMC_IRQHandler
+    IRQ USDHC1_IRQHandler
+    IRQ USDHC2_IRQHandler
+    IRQ USB_OTG2_IRQHandler
+    IRQ USB_OTG1_IRQHandler
+    IRQ ENET_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ XBAR1_IRQ_0_1_IRQHandler
+    IRQ XBAR1_IRQ_2_3_IRQHandler
+    IRQ ADC_ETC_IRQ0_IRQHandler
+    IRQ ADC_ETC_IRQ1_IRQHandler
+    IRQ ADC_ETC_IRQ2_IRQHandler
+    IRQ ADC_ETC_ERROR_IRQ_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ ACMP1_IRQHandler
+    IRQ ACMP2_IRQHandler
+    IRQ ACMP3_IRQHandler
+    IRQ ACMP4_IRQHandler
+    IRQ Reserved143_IRQHandler
+    IRQ Reserved144_IRQHandler
+    IRQ ENC1_IRQHandler
+    IRQ ENC2_IRQHandler
+    IRQ ENC3_IRQHandler
+    IRQ ENC4_IRQHandler
+    IRQ TMR1_IRQHandler
+    IRQ TMR2_IRQHandler
+    IRQ TMR3_IRQHandler
+    IRQ TMR4_IRQHandler
+    IRQ PWM2_0_IRQHandler
+    IRQ PWM2_1_IRQHandler
+    IRQ PWM2_2_IRQHandler
+    IRQ PWM2_3_IRQHandler
+    IRQ PWM2_FAULT_IRQHandler
+    IRQ PWM3_0_IRQHandler
+    IRQ PWM3_1_IRQHandler
+    IRQ PWM3_2_IRQHandler
+    IRQ PWM3_3_IRQHandler
+    IRQ PWM3_FAULT_IRQHandler
+    IRQ PWM4_0_IRQHandler
+    IRQ PWM4_1_IRQHandler
+    IRQ PWM4_2_IRQHandler
+    IRQ PWM4_3_IRQHandler
+    IRQ PWM4_FAULT_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mimxrt1062.s

@@ -0,0 +1,383 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MIMXRT1062.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MIMXRT1062DVL6A
+*/
+
+//     Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_DMA16_IRQHandler
+    .long DMA1_DMA17_IRQHandler
+    .long DMA2_DMA18_IRQHandler
+    .long DMA3_DMA19_IRQHandler
+    .long DMA4_DMA20_IRQHandler
+    .long DMA5_DMA21_IRQHandler
+    .long DMA6_DMA22_IRQHandler
+    .long DMA7_DMA23_IRQHandler
+    .long DMA8_DMA24_IRQHandler
+    .long DMA9_DMA25_IRQHandler
+    .long DMA10_DMA26_IRQHandler
+    .long DMA11_DMA27_IRQHandler
+    .long DMA12_DMA28_IRQHandler
+    .long DMA13_DMA29_IRQHandler
+    .long DMA14_DMA30_IRQHandler
+    .long DMA15_DMA31_IRQHandler
+    .long DMA_ERROR_IRQHandler
+    .long CTI0_ERROR_IRQHandler
+    .long CTI1_ERROR_IRQHandler
+    .long CORE_IRQHandler
+    .long LPUART1_IRQHandler
+    .long LPUART2_IRQHandler
+    .long LPUART3_IRQHandler
+    .long LPUART4_IRQHandler
+    .long LPUART5_IRQHandler
+    .long LPUART6_IRQHandler
+    .long LPUART7_IRQHandler
+    .long LPUART8_IRQHandler
+    .long LPI2C1_IRQHandler
+    .long LPI2C2_IRQHandler
+    .long LPI2C3_IRQHandler
+    .long LPI2C4_IRQHandler
+    .long LPSPI1_IRQHandler
+    .long LPSPI2_IRQHandler
+    .long LPSPI3_IRQHandler
+    .long LPSPI4_IRQHandler
+    .long CAN1_IRQHandler
+    .long CAN2_IRQHandler
+    .long FLEXRAM_IRQHandler
+    .long KPP_IRQHandler
+    .long TSC_DIG_IRQHandler
+    .long GPR_IRQ_IRQHandler
+    .long LCDIF_IRQHandler
+    .long CSI_IRQHandler
+    .long PXP_IRQHandler
+    .long WDOG2_IRQHandler
+    .long SNVS_HP_WRAPPER_IRQHandler
+    .long SNVS_HP_WRAPPER_TZ_IRQHandler
+    .long SNVS_LP_WRAPPER_IRQHandler
+    .long CSU_IRQHandler
+    .long DCP_IRQHandler
+    .long DCP_VMI_IRQHandler
+    .long Reserved68_IRQHandler
+    .long TRNG_IRQHandler
+    .long SJC_IRQHandler
+    .long BEE_IRQHandler
+    .long SAI1_IRQHandler
+    .long SAI2_IRQHandler
+    .long SAI3_RX_IRQHandler
+    .long SAI3_TX_IRQHandler
+    .long SPDIF_IRQHandler
+    .long PMU_EVENT_IRQHandler
+    .long Reserved78_IRQHandler
+    .long TEMP_LOW_HIGH_IRQHandler
+    .long TEMP_PANIC_IRQHandler
+    .long USB_PHY1_IRQHandler
+    .long USB_PHY2_IRQHandler
+    .long ADC1_IRQHandler
+    .long ADC2_IRQHandler
+    .long DCDC_IRQHandler
+    .long Reserved86_IRQHandler
+    .long Reserved87_IRQHandler
+    .long GPIO1_INT0_IRQHandler
+    .long GPIO1_INT1_IRQHandler
+    .long GPIO1_INT2_IRQHandler
+    .long GPIO1_INT3_IRQHandler
+    .long GPIO1_INT4_IRQHandler
+    .long GPIO1_INT5_IRQHandler
+    .long GPIO1_INT6_IRQHandler
+    .long GPIO1_INT7_IRQHandler
+    .long GPIO1_Combined_0_15_IRQHandler
+    .long GPIO1_Combined_16_31_IRQHandler
+    .long GPIO2_Combined_0_15_IRQHandler
+    .long GPIO2_Combined_16_31_IRQHandler
+    .long GPIO3_Combined_0_15_IRQHandler
+    .long GPIO3_Combined_16_31_IRQHandler
+    .long GPIO4_Combined_0_15_IRQHandler
+    .long GPIO4_Combined_16_31_IRQHandler
+    .long GPIO5_Combined_0_15_IRQHandler
+    .long GPIO5_Combined_16_31_IRQHandler
+    .long FLEXIO1_IRQHandler
+    .long FLEXIO2_IRQHandler
+    .long WDOG1_IRQHandler
+    .long RTWDOG_IRQHandler
+    .long EWM_IRQHandler
+    .long CCM_1_IRQHandler
+    .long CCM_2_IRQHandler
+    .long GPC_IRQHandler
+    .long SRC_IRQHandler
+    .long Reserved115_IRQHandler
+    .long GPT1_IRQHandler
+    .long GPT2_IRQHandler
+    .long PWM1_0_IRQHandler
+    .long PWM1_1_IRQHandler
+    .long PWM1_2_IRQHandler
+    .long PWM1_3_IRQHandler
+    .long PWM1_FAULT_IRQHandler
+    .long FLEXSPI2_IRQHandler
+    .long FLEXSPI_IRQHandler
+    .long SEMC_IRQHandler
+    .long USDHC1_IRQHandler
+    .long USDHC2_IRQHandler
+    .long USB_OTG2_IRQHandler
+    .long USB_OTG1_IRQHandler
+    .long ENET_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long XBAR1_IRQ_0_1_IRQHandler
+    .long XBAR1_IRQ_2_3_IRQHandler
+    .long ADC_ETC_IRQ0_IRQHandler
+    .long ADC_ETC_IRQ1_IRQHandler
+    .long ADC_ETC_IRQ2_IRQHandler
+    .long ADC_ETC_ERROR_IRQ_IRQHandler
+    .long PIT_IRQHandler
+    .long ACMP1_IRQHandler
+    .long ACMP2_IRQHandler
+    .long ACMP3_IRQHandler
+    .long ACMP4_IRQHandler
+    .long Reserved143_IRQHandler
+    .long Reserved144_IRQHandler
+    .long ENC1_IRQHandler
+    .long ENC2_IRQHandler
+    .long ENC3_IRQHandler
+    .long ENC4_IRQHandler
+    .long TMR1_IRQHandler
+    .long TMR2_IRQHandler
+    .long TMR3_IRQHandler
+    .long TMR4_IRQHandler
+    .long PWM2_0_IRQHandler
+    .long PWM2_1_IRQHandler
+    .long PWM2_2_IRQHandler
+    .long PWM2_3_IRQHandler
+    .long PWM2_FAULT_IRQHandler
+    .long PWM3_0_IRQHandler
+    .long PWM3_1_IRQHandler
+    .long PWM3_2_IRQHandler
+    .long PWM3_3_IRQHandler
+    .long PWM3_FAULT_IRQHandler
+    .long PWM4_0_IRQHandler
+    .long PWM4_1_IRQHandler
+    .long PWM4_2_IRQHandler
+    .long PWM4_3_IRQHandler
+    .long PWM4_FAULT_IRQHandler
+    .long ENET2_IRQHandler
+    .long ENET2_1588_Timer_IRQHandler
+    .long CAN3_IRQHandler
+    .long Reserved171_IRQHandler
+    .long FLEXIO3_IRQHandler
+    .long GPIO6_7_8_9_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_DMA16_IRQHandler
+    IRQ DMA1_DMA17_IRQHandler
+    IRQ DMA2_DMA18_IRQHandler
+    IRQ DMA3_DMA19_IRQHandler
+    IRQ DMA4_DMA20_IRQHandler
+    IRQ DMA5_DMA21_IRQHandler
+    IRQ DMA6_DMA22_IRQHandler
+    IRQ DMA7_DMA23_IRQHandler
+    IRQ DMA8_DMA24_IRQHandler
+    IRQ DMA9_DMA25_IRQHandler
+    IRQ DMA10_DMA26_IRQHandler
+    IRQ DMA11_DMA27_IRQHandler
+    IRQ DMA12_DMA28_IRQHandler
+    IRQ DMA13_DMA29_IRQHandler
+    IRQ DMA14_DMA30_IRQHandler
+    IRQ DMA15_DMA31_IRQHandler
+    IRQ DMA_ERROR_IRQHandler
+    IRQ CTI0_ERROR_IRQHandler
+    IRQ CTI1_ERROR_IRQHandler
+    IRQ CORE_IRQHandler
+    IRQ LPUART1_IRQHandler
+    IRQ LPUART2_IRQHandler
+    IRQ LPUART3_IRQHandler
+    IRQ LPUART4_IRQHandler
+    IRQ LPUART5_IRQHandler
+    IRQ LPUART6_IRQHandler
+    IRQ LPUART7_IRQHandler
+    IRQ LPUART8_IRQHandler
+    IRQ LPI2C1_IRQHandler
+    IRQ LPI2C2_IRQHandler
+    IRQ LPI2C3_IRQHandler
+    IRQ LPI2C4_IRQHandler
+    IRQ LPSPI1_IRQHandler
+    IRQ LPSPI2_IRQHandler
+    IRQ LPSPI3_IRQHandler
+    IRQ LPSPI4_IRQHandler
+    IRQ CAN1_IRQHandler
+    IRQ CAN2_IRQHandler
+    IRQ FLEXRAM_IRQHandler
+    IRQ KPP_IRQHandler
+    IRQ TSC_DIG_IRQHandler
+    IRQ GPR_IRQ_IRQHandler
+    IRQ LCDIF_IRQHandler
+    IRQ CSI_IRQHandler
+    IRQ PXP_IRQHandler
+    IRQ WDOG2_IRQHandler
+    IRQ SNVS_HP_WRAPPER_IRQHandler
+    IRQ SNVS_HP_WRAPPER_TZ_IRQHandler
+    IRQ SNVS_LP_WRAPPER_IRQHandler
+    IRQ CSU_IRQHandler
+    IRQ DCP_IRQHandler
+    IRQ DCP_VMI_IRQHandler
+    IRQ Reserved68_IRQHandler
+    IRQ TRNG_IRQHandler
+    IRQ SJC_IRQHandler
+    IRQ BEE_IRQHandler
+    IRQ SAI1_IRQHandler
+    IRQ SAI2_IRQHandler
+    IRQ SAI3_RX_IRQHandler
+    IRQ SAI3_TX_IRQHandler
+    IRQ SPDIF_IRQHandler
+    IRQ PMU_EVENT_IRQHandler
+    IRQ Reserved78_IRQHandler
+    IRQ TEMP_LOW_HIGH_IRQHandler
+    IRQ TEMP_PANIC_IRQHandler
+    IRQ USB_PHY1_IRQHandler
+    IRQ USB_PHY2_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ ADC2_IRQHandler
+    IRQ DCDC_IRQHandler
+    IRQ Reserved86_IRQHandler
+    IRQ Reserved87_IRQHandler
+    IRQ GPIO1_INT0_IRQHandler
+    IRQ GPIO1_INT1_IRQHandler
+    IRQ GPIO1_INT2_IRQHandler
+    IRQ GPIO1_INT3_IRQHandler
+    IRQ GPIO1_INT4_IRQHandler
+    IRQ GPIO1_INT5_IRQHandler
+    IRQ GPIO1_INT6_IRQHandler
+    IRQ GPIO1_INT7_IRQHandler
+    IRQ GPIO1_Combined_0_15_IRQHandler
+    IRQ GPIO1_Combined_16_31_IRQHandler
+    IRQ GPIO2_Combined_0_15_IRQHandler
+    IRQ GPIO2_Combined_16_31_IRQHandler
+    IRQ GPIO3_Combined_0_15_IRQHandler
+    IRQ GPIO3_Combined_16_31_IRQHandler
+    IRQ GPIO4_Combined_0_15_IRQHandler
+    IRQ GPIO4_Combined_16_31_IRQHandler
+    IRQ GPIO5_Combined_0_15_IRQHandler
+    IRQ GPIO5_Combined_16_31_IRQHandler
+    IRQ FLEXIO1_IRQHandler
+    IRQ FLEXIO2_IRQHandler
+    IRQ WDOG1_IRQHandler
+    IRQ RTWDOG_IRQHandler
+    IRQ EWM_IRQHandler
+    IRQ CCM_1_IRQHandler
+    IRQ CCM_2_IRQHandler
+    IRQ GPC_IRQHandler
+    IRQ SRC_IRQHandler
+    IRQ Reserved115_IRQHandler
+    IRQ GPT1_IRQHandler
+    IRQ GPT2_IRQHandler
+    IRQ PWM1_0_IRQHandler
+    IRQ PWM1_1_IRQHandler
+    IRQ PWM1_2_IRQHandler
+    IRQ PWM1_3_IRQHandler
+    IRQ PWM1_FAULT_IRQHandler
+    IRQ FLEXSPI2_IRQHandler
+    IRQ FLEXSPI_IRQHandler
+    IRQ SEMC_IRQHandler
+    IRQ USDHC1_IRQHandler
+    IRQ USDHC2_IRQHandler
+    IRQ USB_OTG2_IRQHandler
+    IRQ USB_OTG1_IRQHandler
+    IRQ ENET_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ XBAR1_IRQ_0_1_IRQHandler
+    IRQ XBAR1_IRQ_2_3_IRQHandler
+    IRQ ADC_ETC_IRQ0_IRQHandler
+    IRQ ADC_ETC_IRQ1_IRQHandler
+    IRQ ADC_ETC_IRQ2_IRQHandler
+    IRQ ADC_ETC_ERROR_IRQ_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ ACMP1_IRQHandler
+    IRQ ACMP2_IRQHandler
+    IRQ ACMP3_IRQHandler
+    IRQ ACMP4_IRQHandler
+    IRQ Reserved143_IRQHandler
+    IRQ Reserved144_IRQHandler
+    IRQ ENC1_IRQHandler
+    IRQ ENC2_IRQHandler
+    IRQ ENC3_IRQHandler
+    IRQ ENC4_IRQHandler
+    IRQ TMR1_IRQHandler
+    IRQ TMR2_IRQHandler
+    IRQ TMR3_IRQHandler
+    IRQ TMR4_IRQHandler
+    IRQ PWM2_0_IRQHandler
+    IRQ PWM2_1_IRQHandler
+    IRQ PWM2_2_IRQHandler
+    IRQ PWM2_3_IRQHandler
+    IRQ PWM2_FAULT_IRQHandler
+    IRQ PWM3_0_IRQHandler
+    IRQ PWM3_1_IRQHandler
+    IRQ PWM3_2_IRQHandler
+    IRQ PWM3_3_IRQHandler
+    IRQ PWM3_FAULT_IRQHandler
+    IRQ PWM4_0_IRQHandler
+    IRQ PWM4_1_IRQHandler
+    IRQ PWM4_2_IRQHandler
+    IRQ PWM4_3_IRQHandler
+    IRQ PWM4_FAULT_IRQHandler
+    IRQ ENET2_IRQHandler
+    IRQ ENET2_1588_Timer_IRQHandler
+    IRQ CAN3_IRQHandler
+    IRQ Reserved171_IRQHandler
+    IRQ FLEXIO3_IRQHandler
+    IRQ GPIO6_7_8_9_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mimxrt1064.s

@@ -0,0 +1,383 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MIMXRT1064.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MIMXRT1064DVL6A
+*/
+
+//     Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_DMA16_IRQHandler
+    .long DMA1_DMA17_IRQHandler
+    .long DMA2_DMA18_IRQHandler
+    .long DMA3_DMA19_IRQHandler
+    .long DMA4_DMA20_IRQHandler
+    .long DMA5_DMA21_IRQHandler
+    .long DMA6_DMA22_IRQHandler
+    .long DMA7_DMA23_IRQHandler
+    .long DMA8_DMA24_IRQHandler
+    .long DMA9_DMA25_IRQHandler
+    .long DMA10_DMA26_IRQHandler
+    .long DMA11_DMA27_IRQHandler
+    .long DMA12_DMA28_IRQHandler
+    .long DMA13_DMA29_IRQHandler
+    .long DMA14_DMA30_IRQHandler
+    .long DMA15_DMA31_IRQHandler
+    .long DMA_ERROR_IRQHandler
+    .long CTI0_ERROR_IRQHandler
+    .long CTI1_ERROR_IRQHandler
+    .long CORE_IRQHandler
+    .long LPUART1_IRQHandler
+    .long LPUART2_IRQHandler
+    .long LPUART3_IRQHandler
+    .long LPUART4_IRQHandler
+    .long LPUART5_IRQHandler
+    .long LPUART6_IRQHandler
+    .long LPUART7_IRQHandler
+    .long LPUART8_IRQHandler
+    .long LPI2C1_IRQHandler
+    .long LPI2C2_IRQHandler
+    .long LPI2C3_IRQHandler
+    .long LPI2C4_IRQHandler
+    .long LPSPI1_IRQHandler
+    .long LPSPI2_IRQHandler
+    .long LPSPI3_IRQHandler
+    .long LPSPI4_IRQHandler
+    .long CAN1_IRQHandler
+    .long CAN2_IRQHandler
+    .long FLEXRAM_IRQHandler
+    .long KPP_IRQHandler
+    .long TSC_DIG_IRQHandler
+    .long GPR_IRQ_IRQHandler
+    .long LCDIF_IRQHandler
+    .long CSI_IRQHandler
+    .long PXP_IRQHandler
+    .long WDOG2_IRQHandler
+    .long SNVS_HP_WRAPPER_IRQHandler
+    .long SNVS_HP_WRAPPER_TZ_IRQHandler
+    .long SNVS_LP_WRAPPER_IRQHandler
+    .long CSU_IRQHandler
+    .long DCP_IRQHandler
+    .long DCP_VMI_IRQHandler
+    .long Reserved68_IRQHandler
+    .long TRNG_IRQHandler
+    .long SJC_IRQHandler
+    .long BEE_IRQHandler
+    .long SAI1_IRQHandler
+    .long SAI2_IRQHandler
+    .long SAI3_RX_IRQHandler
+    .long SAI3_TX_IRQHandler
+    .long SPDIF_IRQHandler
+    .long PMU_EVENT_IRQHandler
+    .long Reserved78_IRQHandler
+    .long TEMP_LOW_HIGH_IRQHandler
+    .long TEMP_PANIC_IRQHandler
+    .long USB_PHY1_IRQHandler
+    .long USB_PHY2_IRQHandler
+    .long ADC1_IRQHandler
+    .long ADC2_IRQHandler
+    .long DCDC_IRQHandler
+    .long Reserved86_IRQHandler
+    .long Reserved87_IRQHandler
+    .long GPIO1_INT0_IRQHandler
+    .long GPIO1_INT1_IRQHandler
+    .long GPIO1_INT2_IRQHandler
+    .long GPIO1_INT3_IRQHandler
+    .long GPIO1_INT4_IRQHandler
+    .long GPIO1_INT5_IRQHandler
+    .long GPIO1_INT6_IRQHandler
+    .long GPIO1_INT7_IRQHandler
+    .long GPIO1_Combined_0_15_IRQHandler
+    .long GPIO1_Combined_16_31_IRQHandler
+    .long GPIO2_Combined_0_15_IRQHandler
+    .long GPIO2_Combined_16_31_IRQHandler
+    .long GPIO3_Combined_0_15_IRQHandler
+    .long GPIO3_Combined_16_31_IRQHandler
+    .long GPIO4_Combined_0_15_IRQHandler
+    .long GPIO4_Combined_16_31_IRQHandler
+    .long GPIO5_Combined_0_15_IRQHandler
+    .long GPIO5_Combined_16_31_IRQHandler
+    .long FLEXIO1_IRQHandler
+    .long FLEXIO2_IRQHandler
+    .long WDOG1_IRQHandler
+    .long RTWDOG_IRQHandler
+    .long EWM_IRQHandler
+    .long CCM_1_IRQHandler
+    .long CCM_2_IRQHandler
+    .long GPC_IRQHandler
+    .long SRC_IRQHandler
+    .long Reserved115_IRQHandler
+    .long GPT1_IRQHandler
+    .long GPT2_IRQHandler
+    .long PWM1_0_IRQHandler
+    .long PWM1_1_IRQHandler
+    .long PWM1_2_IRQHandler
+    .long PWM1_3_IRQHandler
+    .long PWM1_FAULT_IRQHandler
+    .long FLEXSPI2_IRQHandler
+    .long FLEXSPI_IRQHandler
+    .long SEMC_IRQHandler
+    .long USDHC1_IRQHandler
+    .long USDHC2_IRQHandler
+    .long USB_OTG2_IRQHandler
+    .long USB_OTG1_IRQHandler
+    .long ENET_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long XBAR1_IRQ_0_1_IRQHandler
+    .long XBAR1_IRQ_2_3_IRQHandler
+    .long ADC_ETC_IRQ0_IRQHandler
+    .long ADC_ETC_IRQ1_IRQHandler
+    .long ADC_ETC_IRQ2_IRQHandler
+    .long ADC_ETC_ERROR_IRQ_IRQHandler
+    .long PIT_IRQHandler
+    .long ACMP1_IRQHandler
+    .long ACMP2_IRQHandler
+    .long ACMP3_IRQHandler
+    .long ACMP4_IRQHandler
+    .long Reserved143_IRQHandler
+    .long Reserved144_IRQHandler
+    .long ENC1_IRQHandler
+    .long ENC2_IRQHandler
+    .long ENC3_IRQHandler
+    .long ENC4_IRQHandler
+    .long TMR1_IRQHandler
+    .long TMR2_IRQHandler
+    .long TMR3_IRQHandler
+    .long TMR4_IRQHandler
+    .long PWM2_0_IRQHandler
+    .long PWM2_1_IRQHandler
+    .long PWM2_2_IRQHandler
+    .long PWM2_3_IRQHandler
+    .long PWM2_FAULT_IRQHandler
+    .long PWM3_0_IRQHandler
+    .long PWM3_1_IRQHandler
+    .long PWM3_2_IRQHandler
+    .long PWM3_3_IRQHandler
+    .long PWM3_FAULT_IRQHandler
+    .long PWM4_0_IRQHandler
+    .long PWM4_1_IRQHandler
+    .long PWM4_2_IRQHandler
+    .long PWM4_3_IRQHandler
+    .long PWM4_FAULT_IRQHandler
+    .long ENET2_IRQHandler
+    .long ENET2_1588_Timer_IRQHandler
+    .long CAN3_IRQHandler
+    .long Reserved171_IRQHandler
+    .long FLEXIO3_IRQHandler
+    .long GPIO6_7_8_9_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_DMA16_IRQHandler
+    IRQ DMA1_DMA17_IRQHandler
+    IRQ DMA2_DMA18_IRQHandler
+    IRQ DMA3_DMA19_IRQHandler
+    IRQ DMA4_DMA20_IRQHandler
+    IRQ DMA5_DMA21_IRQHandler
+    IRQ DMA6_DMA22_IRQHandler
+    IRQ DMA7_DMA23_IRQHandler
+    IRQ DMA8_DMA24_IRQHandler
+    IRQ DMA9_DMA25_IRQHandler
+    IRQ DMA10_DMA26_IRQHandler
+    IRQ DMA11_DMA27_IRQHandler
+    IRQ DMA12_DMA28_IRQHandler
+    IRQ DMA13_DMA29_IRQHandler
+    IRQ DMA14_DMA30_IRQHandler
+    IRQ DMA15_DMA31_IRQHandler
+    IRQ DMA_ERROR_IRQHandler
+    IRQ CTI0_ERROR_IRQHandler
+    IRQ CTI1_ERROR_IRQHandler
+    IRQ CORE_IRQHandler
+    IRQ LPUART1_IRQHandler
+    IRQ LPUART2_IRQHandler
+    IRQ LPUART3_IRQHandler
+    IRQ LPUART4_IRQHandler
+    IRQ LPUART5_IRQHandler
+    IRQ LPUART6_IRQHandler
+    IRQ LPUART7_IRQHandler
+    IRQ LPUART8_IRQHandler
+    IRQ LPI2C1_IRQHandler
+    IRQ LPI2C2_IRQHandler
+    IRQ LPI2C3_IRQHandler
+    IRQ LPI2C4_IRQHandler
+    IRQ LPSPI1_IRQHandler
+    IRQ LPSPI2_IRQHandler
+    IRQ LPSPI3_IRQHandler
+    IRQ LPSPI4_IRQHandler
+    IRQ CAN1_IRQHandler
+    IRQ CAN2_IRQHandler
+    IRQ FLEXRAM_IRQHandler
+    IRQ KPP_IRQHandler
+    IRQ TSC_DIG_IRQHandler
+    IRQ GPR_IRQ_IRQHandler
+    IRQ LCDIF_IRQHandler
+    IRQ CSI_IRQHandler
+    IRQ PXP_IRQHandler
+    IRQ WDOG2_IRQHandler
+    IRQ SNVS_HP_WRAPPER_IRQHandler
+    IRQ SNVS_HP_WRAPPER_TZ_IRQHandler
+    IRQ SNVS_LP_WRAPPER_IRQHandler
+    IRQ CSU_IRQHandler
+    IRQ DCP_IRQHandler
+    IRQ DCP_VMI_IRQHandler
+    IRQ Reserved68_IRQHandler
+    IRQ TRNG_IRQHandler
+    IRQ SJC_IRQHandler
+    IRQ BEE_IRQHandler
+    IRQ SAI1_IRQHandler
+    IRQ SAI2_IRQHandler
+    IRQ SAI3_RX_IRQHandler
+    IRQ SAI3_TX_IRQHandler
+    IRQ SPDIF_IRQHandler
+    IRQ PMU_EVENT_IRQHandler
+    IRQ Reserved78_IRQHandler
+    IRQ TEMP_LOW_HIGH_IRQHandler
+    IRQ TEMP_PANIC_IRQHandler
+    IRQ USB_PHY1_IRQHandler
+    IRQ USB_PHY2_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ ADC2_IRQHandler
+    IRQ DCDC_IRQHandler
+    IRQ Reserved86_IRQHandler
+    IRQ Reserved87_IRQHandler
+    IRQ GPIO1_INT0_IRQHandler
+    IRQ GPIO1_INT1_IRQHandler
+    IRQ GPIO1_INT2_IRQHandler
+    IRQ GPIO1_INT3_IRQHandler
+    IRQ GPIO1_INT4_IRQHandler
+    IRQ GPIO1_INT5_IRQHandler
+    IRQ GPIO1_INT6_IRQHandler
+    IRQ GPIO1_INT7_IRQHandler
+    IRQ GPIO1_Combined_0_15_IRQHandler
+    IRQ GPIO1_Combined_16_31_IRQHandler
+    IRQ GPIO2_Combined_0_15_IRQHandler
+    IRQ GPIO2_Combined_16_31_IRQHandler
+    IRQ GPIO3_Combined_0_15_IRQHandler
+    IRQ GPIO3_Combined_16_31_IRQHandler
+    IRQ GPIO4_Combined_0_15_IRQHandler
+    IRQ GPIO4_Combined_16_31_IRQHandler
+    IRQ GPIO5_Combined_0_15_IRQHandler
+    IRQ GPIO5_Combined_16_31_IRQHandler
+    IRQ FLEXIO1_IRQHandler
+    IRQ FLEXIO2_IRQHandler
+    IRQ WDOG1_IRQHandler
+    IRQ RTWDOG_IRQHandler
+    IRQ EWM_IRQHandler
+    IRQ CCM_1_IRQHandler
+    IRQ CCM_2_IRQHandler
+    IRQ GPC_IRQHandler
+    IRQ SRC_IRQHandler
+    IRQ Reserved115_IRQHandler
+    IRQ GPT1_IRQHandler
+    IRQ GPT2_IRQHandler
+    IRQ PWM1_0_IRQHandler
+    IRQ PWM1_1_IRQHandler
+    IRQ PWM1_2_IRQHandler
+    IRQ PWM1_3_IRQHandler
+    IRQ PWM1_FAULT_IRQHandler
+    IRQ FLEXSPI2_IRQHandler
+    IRQ FLEXSPI_IRQHandler
+    IRQ SEMC_IRQHandler
+    IRQ USDHC1_IRQHandler
+    IRQ USDHC2_IRQHandler
+    IRQ USB_OTG2_IRQHandler
+    IRQ USB_OTG1_IRQHandler
+    IRQ ENET_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ XBAR1_IRQ_0_1_IRQHandler
+    IRQ XBAR1_IRQ_2_3_IRQHandler
+    IRQ ADC_ETC_IRQ0_IRQHandler
+    IRQ ADC_ETC_IRQ1_IRQHandler
+    IRQ ADC_ETC_IRQ2_IRQHandler
+    IRQ ADC_ETC_ERROR_IRQ_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ ACMP1_IRQHandler
+    IRQ ACMP2_IRQHandler
+    IRQ ACMP3_IRQHandler
+    IRQ ACMP4_IRQHandler
+    IRQ Reserved143_IRQHandler
+    IRQ Reserved144_IRQHandler
+    IRQ ENC1_IRQHandler
+    IRQ ENC2_IRQHandler
+    IRQ ENC3_IRQHandler
+    IRQ ENC4_IRQHandler
+    IRQ TMR1_IRQHandler
+    IRQ TMR2_IRQHandler
+    IRQ TMR3_IRQHandler
+    IRQ TMR4_IRQHandler
+    IRQ PWM2_0_IRQHandler
+    IRQ PWM2_1_IRQHandler
+    IRQ PWM2_2_IRQHandler
+    IRQ PWM2_3_IRQHandler
+    IRQ PWM2_FAULT_IRQHandler
+    IRQ PWM3_0_IRQHandler
+    IRQ PWM3_1_IRQHandler
+    IRQ PWM3_2_IRQHandler
+    IRQ PWM3_3_IRQHandler
+    IRQ PWM3_FAULT_IRQHandler
+    IRQ PWM4_0_IRQHandler
+    IRQ PWM4_1_IRQHandler
+    IRQ PWM4_2_IRQHandler
+    IRQ PWM4_3_IRQHandler
+    IRQ PWM4_FAULT_IRQHandler
+    IRQ ENET2_IRQHandler
+    IRQ ENET2_1588_Timer_IRQHandler
+    IRQ CAN3_IRQHandler
+    IRQ Reserved171_IRQHandler
+    IRQ FLEXIO3_IRQHandler
+    IRQ GPIO6_7_8_9_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mk22f25612.s

@@ -0,0 +1,218 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MK22F25612.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MK22F25612 NXP Microcontroller
+*/
+
+//     Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:
+//     o Redistributions of source code must retain the above copyright notice, this list
+//     of conditions and the following disclaimer.
+//     o Redistributions in binary form must reproduce the above copyright notice, this
+//     list of conditions and the following disclaimer in the documentation and/or
+//     other materials provided with the distribution.
+//     o Neither the name of the copyright holder nor the names of its
+//     contributors may be used to endorse or promote products derived from this
+//     software without specific prior written permission.
+//     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+//     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+//     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+//     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+//     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+//     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+//     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+//     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+//     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_IRQHandler
+    .long DMA1_IRQHandler
+    .long DMA2_IRQHandler
+    .long DMA3_IRQHandler
+    .long DMA4_IRQHandler
+    .long DMA5_IRQHandler
+    .long DMA6_IRQHandler
+    .long DMA7_IRQHandler
+    .long DMA8_IRQHandler
+    .long DMA9_IRQHandler
+    .long DMA10_IRQHandler
+    .long DMA11_IRQHandler
+    .long DMA12_IRQHandler
+    .long DMA13_IRQHandler
+    .long DMA14_IRQHandler
+    .long DMA15_IRQHandler
+    .long DMA_Error_IRQHandler
+    .long MCM_IRQHandler
+    .long FTF_IRQHandler
+    .long Read_Collision_IRQHandler
+    .long LVD_LVW_IRQHandler
+    .long LLWU_IRQHandler
+    .long WDOG_EWM_IRQHandler
+    .long RNG_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2S0_Tx_IRQHandler
+    .long I2S0_Rx_IRQHandler
+    .long LPUART0_IRQHandler
+    .long UART0_RX_TX_IRQHandler
+    .long UART0_ERR_IRQHandler
+    .long UART1_RX_TX_IRQHandler
+    .long UART1_ERR_IRQHandler
+    .long UART2_RX_TX_IRQHandler
+    .long UART2_ERR_IRQHandler
+    .long 0
+    .long 0
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+    .long FTM0_IRQHandler
+    .long FTM1_IRQHandler
+    .long FTM2_IRQHandler
+    .long 0
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT0_IRQHandler
+    .long PIT1_IRQHandler
+    .long PIT2_IRQHandler
+    .long PIT3_IRQHandler
+    .long PDB0_IRQHandler
+    .long USB0_IRQHandler
+    .long 0
+    .long 0
+    .long DAC0_IRQHandler
+    .long 0
+    .long LPTMR0_IRQHandler
+    .long PORTA_IRQHandler
+    .long PORTB_IRQHandler
+    .long PORTC_IRQHandler
+    .long PORTD_IRQHandler
+    .long PORTE_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long ADC1_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_IRQHandler
+    IRQ DMA1_IRQHandler
+    IRQ DMA2_IRQHandler
+    IRQ DMA3_IRQHandler
+    IRQ DMA4_IRQHandler
+    IRQ DMA5_IRQHandler
+    IRQ DMA6_IRQHandler
+    IRQ DMA7_IRQHandler
+    IRQ DMA8_IRQHandler
+    IRQ DMA9_IRQHandler
+    IRQ DMA10_IRQHandler
+    IRQ DMA11_IRQHandler
+    IRQ DMA12_IRQHandler
+    IRQ DMA13_IRQHandler
+    IRQ DMA14_IRQHandler
+    IRQ DMA15_IRQHandler
+    IRQ DMA_Error_IRQHandler
+    IRQ MCM_IRQHandler
+    IRQ FTF_IRQHandler
+    IRQ Read_Collision_IRQHandler
+    IRQ LVD_LVW_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ WDOG_EWM_IRQHandler
+    IRQ RNG_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2S0_Tx_IRQHandler
+    IRQ I2S0_Rx_IRQHandler
+    IRQ LPUART0_IRQHandler
+    IRQ UART0_RX_TX_IRQHandler
+    IRQ UART0_ERR_IRQHandler
+    IRQ UART1_RX_TX_IRQHandler
+    IRQ UART1_ERR_IRQHandler
+    IRQ UART2_RX_TX_IRQHandler
+    IRQ UART2_ERR_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+    IRQ FTM0_IRQHandler
+    IRQ FTM1_IRQHandler
+    IRQ FTM2_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT0_IRQHandler
+    IRQ PIT1_IRQHandler
+    IRQ PIT2_IRQHandler
+    IRQ PIT3_IRQHandler
+    IRQ PDB0_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTB_IRQHandler
+    IRQ PORTC_IRQHandler
+    IRQ PORTD_IRQHandler
+    IRQ PORTE_IRQHandler
+    IRQ ADC1_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mk22f51212.s

@@ -0,0 +1,220 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MK22F51212.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MK22F51212 NXP Microcontroller
+*/
+
+//     Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:
+//     o Redistributions of source code must retain the above copyright notice, this list
+//     of conditions and the following disclaimer.
+//     o Redistributions in binary form must reproduce the above copyright notice, this
+//     list of conditions and the following disclaimer in the documentation and/or
+//     other materials provided with the distribution.
+//     o Neither the name of the copyright holder nor the names of its
+//     contributors may be used to endorse or promote products derived from this
+//     software without specific prior written permission.
+//     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+//     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+//     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+//     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+//     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+//     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+//     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+//     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+//     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_IRQHandler
+    .long DMA1_IRQHandler
+    .long DMA2_IRQHandler
+    .long DMA3_IRQHandler
+    .long DMA4_IRQHandler
+    .long DMA5_IRQHandler
+    .long DMA6_IRQHandler
+    .long DMA7_IRQHandler
+    .long DMA8_IRQHandler
+    .long DMA9_IRQHandler
+    .long DMA10_IRQHandler
+    .long DMA11_IRQHandler
+    .long DMA12_IRQHandler
+    .long DMA13_IRQHandler
+    .long DMA14_IRQHandler
+    .long DMA15_IRQHandler
+    .long DMA_Error_IRQHandler
+    .long MCM_IRQHandler
+    .long FTF_IRQHandler
+    .long Read_Collision_IRQHandler
+    .long LVD_LVW_IRQHandler
+    .long LLWU_IRQHandler
+    .long WDOG_EWM_IRQHandler
+    .long RNG_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2S0_Tx_IRQHandler
+    .long I2S0_Rx_IRQHandler
+    .long LPUART0_IRQHandler
+    .long UART0_RX_TX_IRQHandler
+    .long UART0_ERR_IRQHandler
+    .long UART1_RX_TX_IRQHandler
+    .long UART1_ERR_IRQHandler
+    .long UART2_RX_TX_IRQHandler
+    .long UART2_ERR_IRQHandler
+    .long 0
+    .long 0
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+    .long FTM0_IRQHandler
+    .long FTM1_IRQHandler
+    .long FTM2_IRQHandler
+    .long 0
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT0_IRQHandler
+    .long PIT1_IRQHandler
+    .long PIT2_IRQHandler
+    .long PIT3_IRQHandler
+    .long PDB0_IRQHandler
+    .long USB0_IRQHandler
+    .long 0
+    .long 0
+    .long DAC0_IRQHandler
+    .long 0
+    .long LPTMR0_IRQHandler
+    .long PORTA_IRQHandler
+    .long PORTB_IRQHandler
+    .long PORTC_IRQHandler
+    .long PORTD_IRQHandler
+    .long PORTE_IRQHandler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long FTM3_IRQHandler
+    .long DAC1_IRQHandler
+    .long ADC1_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_IRQHandler
+    IRQ DMA1_IRQHandler
+    IRQ DMA2_IRQHandler
+    IRQ DMA3_IRQHandler
+    IRQ DMA4_IRQHandler
+    IRQ DMA5_IRQHandler
+    IRQ DMA6_IRQHandler
+    IRQ DMA7_IRQHandler
+    IRQ DMA8_IRQHandler
+    IRQ DMA9_IRQHandler
+    IRQ DMA10_IRQHandler
+    IRQ DMA11_IRQHandler
+    IRQ DMA12_IRQHandler
+    IRQ DMA13_IRQHandler
+    IRQ DMA14_IRQHandler
+    IRQ DMA15_IRQHandler
+    IRQ DMA_Error_IRQHandler
+    IRQ MCM_IRQHandler
+    IRQ FTF_IRQHandler
+    IRQ Read_Collision_IRQHandler
+    IRQ LVD_LVW_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ WDOG_EWM_IRQHandler
+    IRQ RNG_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2S0_Tx_IRQHandler
+    IRQ I2S0_Rx_IRQHandler
+    IRQ LPUART0_IRQHandler
+    IRQ UART0_RX_TX_IRQHandler
+    IRQ UART0_ERR_IRQHandler
+    IRQ UART1_RX_TX_IRQHandler
+    IRQ UART1_ERR_IRQHandler
+    IRQ UART2_RX_TX_IRQHandler
+    IRQ UART2_ERR_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+    IRQ FTM0_IRQHandler
+    IRQ FTM1_IRQHandler
+    IRQ FTM2_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT0_IRQHandler
+    IRQ PIT1_IRQHandler
+    IRQ PIT2_IRQHandler
+    IRQ PIT3_IRQHandler
+    IRQ PDB0_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTB_IRQHandler
+    IRQ PORTC_IRQHandler
+    IRQ PORTD_IRQHandler
+    IRQ PORTE_IRQHandler
+    IRQ FTM3_IRQHandler
+    IRQ DAC1_IRQHandler
+    IRQ ADC1_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mk64f12.s

@@ -0,0 +1,236 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MK64F12.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MK64F12 NXP Microcontroller
+*/
+
+//     Copyright 2016-2018 NXP SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_IRQHandler
+    .long DMA1_IRQHandler
+    .long DMA2_IRQHandler
+    .long DMA3_IRQHandler
+    .long DMA4_IRQHandler
+    .long DMA5_IRQHandler
+    .long DMA6_IRQHandler
+    .long DMA7_IRQHandler
+    .long DMA8_IRQHandler
+    .long DMA9_IRQHandler
+    .long DMA10_IRQHandler
+    .long DMA11_IRQHandler
+    .long DMA12_IRQHandler
+    .long DMA13_IRQHandler
+    .long DMA14_IRQHandler
+    .long DMA15_IRQHandler
+    .long DMA_Error_IRQHandler
+    .long MCM_IRQHandler
+    .long FTFE_IRQHandler
+    .long Read_Collision_IRQHandler
+    .long LVD_LVW_IRQHandler
+    .long LLWU_IRQHandler
+    .long WDOG_EWM_IRQHandler
+    .long RNG_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2S0_Tx_IRQHandler
+    .long I2S0_Rx_IRQHandler
+    .long UART0_LON_IRQHandler
+    .long UART0_RX_TX_IRQHandler
+    .long UART0_ERR_IRQHandler
+    .long UART1_RX_TX_IRQHandler
+    .long UART1_ERR_IRQHandler
+    .long UART2_RX_TX_IRQHandler
+    .long UART2_ERR_IRQHandler
+    .long UART3_RX_TX_IRQHandler
+    .long UART3_ERR_IRQHandler
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+    .long FTM0_IRQHandler
+    .long FTM1_IRQHandler
+    .long FTM2_IRQHandler
+    .long CMT_IRQHandler
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT0_IRQHandler
+    .long PIT1_IRQHandler
+    .long PIT2_IRQHandler
+    .long PIT3_IRQHandler
+    .long PDB0_IRQHandler
+    .long USB0_IRQHandler
+    .long USBDCD_IRQHandler
+    .long 0
+    .long DAC0_IRQHandler
+    .long 0
+    .long LPTMR0_IRQHandler
+    .long PORTA_IRQHandler
+    .long PORTB_IRQHandler
+    .long PORTC_IRQHandler
+    .long PORTD_IRQHandler
+    .long PORTE_IRQHandler
+    .long 0
+    .long SPI2_IRQHandler
+    .long UART4_RX_TX_IRQHandler
+    .long UART4_ERR_IRQHandler
+    .long UART5_RX_TX_IRQHandler
+    .long UART5_ERR_IRQHandler
+    .long CMP2_IRQHandler
+    .long FTM3_IRQHandler
+    .long DAC1_IRQHandler
+    .long ADC1_IRQHandler
+    .long I2C2_IRQHandler
+    .long CAN0_ORed_Message_buffer_IRQHandler
+    .long CAN0_Bus_Off_IRQHandler
+    .long CAN0_Error_IRQHandler
+    .long CAN0_Tx_Warning_IRQHandler
+    .long CAN0_Rx_Warning_IRQHandler
+    .long CAN0_Wake_Up_IRQHandler
+    .long SDHC_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long ENET_Transmit_IRQHandler
+    .long ENET_Receive_IRQHandler
+    .long ENET_Error_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_IRQHandler
+    IRQ DMA1_IRQHandler
+    IRQ DMA2_IRQHandler
+    IRQ DMA3_IRQHandler
+    IRQ DMA4_IRQHandler
+    IRQ DMA5_IRQHandler
+    IRQ DMA6_IRQHandler
+    IRQ DMA7_IRQHandler
+    IRQ DMA8_IRQHandler
+    IRQ DMA9_IRQHandler
+    IRQ DMA10_IRQHandler
+    IRQ DMA11_IRQHandler
+    IRQ DMA12_IRQHandler
+    IRQ DMA13_IRQHandler
+    IRQ DMA14_IRQHandler
+    IRQ DMA15_IRQHandler
+    IRQ DMA_Error_IRQHandler
+    IRQ MCM_IRQHandler
+    IRQ FTFE_IRQHandler
+    IRQ Read_Collision_IRQHandler
+    IRQ LVD_LVW_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ WDOG_EWM_IRQHandler
+    IRQ RNG_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2S0_Tx_IRQHandler
+    IRQ I2S0_Rx_IRQHandler
+    IRQ UART0_LON_IRQHandler
+    IRQ UART0_RX_TX_IRQHandler
+    IRQ UART0_ERR_IRQHandler
+    IRQ UART1_RX_TX_IRQHandler
+    IRQ UART1_ERR_IRQHandler
+    IRQ UART2_RX_TX_IRQHandler
+    IRQ UART2_ERR_IRQHandler
+    IRQ UART3_RX_TX_IRQHandler
+    IRQ UART3_ERR_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+    IRQ FTM0_IRQHandler
+    IRQ FTM1_IRQHandler
+    IRQ FTM2_IRQHandler
+    IRQ CMT_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT0_IRQHandler
+    IRQ PIT1_IRQHandler
+    IRQ PIT2_IRQHandler
+    IRQ PIT3_IRQHandler
+    IRQ PDB0_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ USBDCD_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTB_IRQHandler
+    IRQ PORTC_IRQHandler
+    IRQ PORTD_IRQHandler
+    IRQ PORTE_IRQHandler
+    IRQ SPI2_IRQHandler
+    IRQ UART4_RX_TX_IRQHandler
+    IRQ UART4_ERR_IRQHandler
+    IRQ UART5_RX_TX_IRQHandler
+    IRQ UART5_ERR_IRQHandler
+    IRQ CMP2_IRQHandler
+    IRQ FTM3_IRQHandler
+    IRQ DAC1_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ CAN0_ORed_Message_buffer_IRQHandler
+    IRQ CAN0_Bus_Off_IRQHandler
+    IRQ CAN0_Error_IRQHandler
+    IRQ CAN0_Tx_Warning_IRQHandler
+    IRQ CAN0_Rx_Warning_IRQHandler
+    IRQ CAN0_Wake_Up_IRQHandler
+    IRQ SDHC_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ ENET_Transmit_IRQHandler
+    IRQ ENET_Receive_IRQHandler
+    IRQ ENET_Error_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mk65f18.s

@@ -0,0 +1,261 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MK65F18.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MK65F18 NXP Microcontroller
+*/
+
+//     Copyright 2016-2018 NXP SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_DMA16_IRQHandler
+    .long DMA1_DMA17_IRQHandler
+    .long DMA2_DMA18_IRQHandler
+    .long DMA3_DMA19_IRQHandler
+    .long DMA4_DMA20_IRQHandler
+    .long DMA5_DMA21_IRQHandler
+    .long DMA6_DMA22_IRQHandler
+    .long DMA7_DMA23_IRQHandler
+    .long DMA8_DMA24_IRQHandler
+    .long DMA9_DMA25_IRQHandler
+    .long DMA10_DMA26_IRQHandler
+    .long DMA11_DMA27_IRQHandler
+    .long DMA12_DMA28_IRQHandler
+    .long DMA13_DMA29_IRQHandler
+    .long DMA14_DMA30_IRQHandler
+    .long DMA15_DMA31_IRQHandler
+    .long DMA_Error_IRQHandler
+    .long MCM_IRQHandler
+    .long FTFE_IRQHandler
+    .long Read_Collision_IRQHandler
+    .long LVD_LVW_IRQHandler
+    .long LLWU_IRQHandler
+    .long WDOG_EWM_IRQHandler
+    .long RNG_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2S0_Tx_IRQHandler
+    .long I2S0_Rx_IRQHandler
+    .long 0
+    .long UART0_RX_TX_IRQHandler
+    .long UART0_ERR_IRQHandler
+    .long UART1_RX_TX_IRQHandler
+    .long UART1_ERR_IRQHandler
+    .long UART2_RX_TX_IRQHandler
+    .long UART2_ERR_IRQHandler
+    .long UART3_RX_TX_IRQHandler
+    .long UART3_ERR_IRQHandler
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+    .long FTM0_IRQHandler
+    .long FTM1_IRQHandler
+    .long FTM2_IRQHandler
+    .long CMT_IRQHandler
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT0_IRQHandler
+    .long PIT1_IRQHandler
+    .long PIT2_IRQHandler
+    .long PIT3_IRQHandler
+    .long PDB0_IRQHandler
+    .long USB0_IRQHandler
+    .long USBDCD_IRQHandler
+    .long 0
+    .long DAC0_IRQHandler
+    .long 0
+    .long LPTMR0_IRQHandler
+    .long PORTA_IRQHandler
+    .long PORTB_IRQHandler
+    .long PORTC_IRQHandler
+    .long PORTD_IRQHandler
+    .long PORTE_IRQHandler
+    .long 0
+    .long SPI2_IRQHandler
+    .long UART4_RX_TX_IRQHandler
+    .long UART4_ERR_IRQHandler
+    .long 0
+    .long 0
+    .long CMP2_IRQHandler
+    .long FTM3_IRQHandler
+    .long DAC1_IRQHandler
+    .long ADC1_IRQHandler
+    .long I2C2_IRQHandler
+    .long CAN0_ORed_Message_buffer_IRQHandler
+    .long CAN0_Bus_Off_IRQHandler
+    .long CAN0_Error_IRQHandler
+    .long CAN0_Tx_Warning_IRQHandler
+    .long CAN0_Rx_Warning_IRQHandler
+    .long CAN0_Wake_Up_IRQHandler
+    .long SDHC_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long ENET_Transmit_IRQHandler
+    .long ENET_Receive_IRQHandler
+    .long ENET_Error_IRQHandler
+    .long LPUART0_IRQHandler
+    .long TSI0_IRQHandler
+    .long TPM1_IRQHandler
+    .long TPM2_IRQHandler
+    .long USBHSDCD_IRQHandler
+    .long I2C3_IRQHandler
+    .long CMP3_IRQHandler
+    .long USBHS_IRQHandler
+    .long CAN1_ORed_Message_buffer_IRQHandler
+    .long CAN1_Bus_Off_IRQHandler
+    .long CAN1_Error_IRQHandler
+    .long CAN1_Tx_Warning_IRQHandler
+    .long CAN1_Rx_Warning_IRQHandler
+    .long CAN1_Wake_Up_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_DMA16_IRQHandler
+    IRQ DMA1_DMA17_IRQHandler
+    IRQ DMA2_DMA18_IRQHandler
+    IRQ DMA3_DMA19_IRQHandler
+    IRQ DMA4_DMA20_IRQHandler
+    IRQ DMA5_DMA21_IRQHandler
+    IRQ DMA6_DMA22_IRQHandler
+    IRQ DMA7_DMA23_IRQHandler
+    IRQ DMA8_DMA24_IRQHandler
+    IRQ DMA9_DMA25_IRQHandler
+    IRQ DMA10_DMA26_IRQHandler
+    IRQ DMA11_DMA27_IRQHandler
+    IRQ DMA12_DMA28_IRQHandler
+    IRQ DMA13_DMA29_IRQHandler
+    IRQ DMA14_DMA30_IRQHandler
+    IRQ DMA15_DMA31_IRQHandler
+    IRQ DMA_Error_IRQHandler
+    IRQ MCM_IRQHandler
+    IRQ FTFE_IRQHandler
+    IRQ Read_Collision_IRQHandler
+    IRQ LVD_LVW_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ WDOG_EWM_IRQHandler
+    IRQ RNG_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2S0_Tx_IRQHandler
+    IRQ I2S0_Rx_IRQHandler
+    IRQ UART0_RX_TX_IRQHandler
+    IRQ UART0_ERR_IRQHandler
+    IRQ UART1_RX_TX_IRQHandler
+    IRQ UART1_ERR_IRQHandler
+    IRQ UART2_RX_TX_IRQHandler
+    IRQ UART2_ERR_IRQHandler
+    IRQ UART3_RX_TX_IRQHandler
+    IRQ UART3_ERR_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+    IRQ FTM0_IRQHandler
+    IRQ FTM1_IRQHandler
+    IRQ FTM2_IRQHandler
+    IRQ CMT_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT0_IRQHandler
+    IRQ PIT1_IRQHandler
+    IRQ PIT2_IRQHandler
+    IRQ PIT3_IRQHandler
+    IRQ PDB0_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ USBDCD_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTB_IRQHandler
+    IRQ PORTC_IRQHandler
+    IRQ PORTD_IRQHandler
+    IRQ PORTE_IRQHandler
+    IRQ SPI2_IRQHandler
+    IRQ UART4_RX_TX_IRQHandler
+    IRQ UART4_ERR_IRQHandler
+    IRQ CMP2_IRQHandler
+    IRQ FTM3_IRQHandler
+    IRQ DAC1_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ CAN0_ORed_Message_buffer_IRQHandler
+    IRQ CAN0_Bus_Off_IRQHandler
+    IRQ CAN0_Error_IRQHandler
+    IRQ CAN0_Tx_Warning_IRQHandler
+    IRQ CAN0_Rx_Warning_IRQHandler
+    IRQ CAN0_Wake_Up_IRQHandler
+    IRQ SDHC_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ ENET_Transmit_IRQHandler
+    IRQ ENET_Receive_IRQHandler
+    IRQ ENET_Error_IRQHandler
+    IRQ LPUART0_IRQHandler
+    IRQ TSI0_IRQHandler
+    IRQ TPM1_IRQHandler
+    IRQ TPM2_IRQHandler
+    IRQ USBHSDCD_IRQHandler
+    IRQ I2C3_IRQHandler
+    IRQ CMP3_IRQHandler
+    IRQ USBHS_IRQHandler
+    IRQ CAN1_ORed_Message_buffer_IRQHandler
+    IRQ CAN1_Bus_Off_IRQHandler
+    IRQ CAN1_Error_IRQHandler
+    IRQ CAN1_Tx_Warning_IRQHandler
+    IRQ CAN1_Rx_Warning_IRQHandler
+    IRQ CAN1_Wake_Up_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mk66f18.s

@@ -0,0 +1,261 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MK66F18.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MK66F18 NXP Microcontroller
+*/
+
+//     Copyright 2016-2018 NXP SPDX-License-Identifier: BSD-3-Clause
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_DMA16_IRQHandler
+    .long DMA1_DMA17_IRQHandler
+    .long DMA2_DMA18_IRQHandler
+    .long DMA3_DMA19_IRQHandler
+    .long DMA4_DMA20_IRQHandler
+    .long DMA5_DMA21_IRQHandler
+    .long DMA6_DMA22_IRQHandler
+    .long DMA7_DMA23_IRQHandler
+    .long DMA8_DMA24_IRQHandler
+    .long DMA9_DMA25_IRQHandler
+    .long DMA10_DMA26_IRQHandler
+    .long DMA11_DMA27_IRQHandler
+    .long DMA12_DMA28_IRQHandler
+    .long DMA13_DMA29_IRQHandler
+    .long DMA14_DMA30_IRQHandler
+    .long DMA15_DMA31_IRQHandler
+    .long DMA_Error_IRQHandler
+    .long MCM_IRQHandler
+    .long FTFE_IRQHandler
+    .long Read_Collision_IRQHandler
+    .long LVD_LVW_IRQHandler
+    .long LLWU_IRQHandler
+    .long WDOG_EWM_IRQHandler
+    .long RNG_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long I2S0_Tx_IRQHandler
+    .long I2S0_Rx_IRQHandler
+    .long 0
+    .long UART0_RX_TX_IRQHandler
+    .long UART0_ERR_IRQHandler
+    .long UART1_RX_TX_IRQHandler
+    .long UART1_ERR_IRQHandler
+    .long UART2_RX_TX_IRQHandler
+    .long UART2_ERR_IRQHandler
+    .long UART3_RX_TX_IRQHandler
+    .long UART3_ERR_IRQHandler
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long CMP1_IRQHandler
+    .long FTM0_IRQHandler
+    .long FTM1_IRQHandler
+    .long FTM2_IRQHandler
+    .long CMT_IRQHandler
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT0_IRQHandler
+    .long PIT1_IRQHandler
+    .long PIT2_IRQHandler
+    .long PIT3_IRQHandler
+    .long PDB0_IRQHandler
+    .long USB0_IRQHandler
+    .long USBDCD_IRQHandler
+    .long 0
+    .long DAC0_IRQHandler
+    .long 0
+    .long LPTMR0_IRQHandler
+    .long PORTA_IRQHandler
+    .long PORTB_IRQHandler
+    .long PORTC_IRQHandler
+    .long PORTD_IRQHandler
+    .long PORTE_IRQHandler
+    .long 0
+    .long SPI2_IRQHandler
+    .long UART4_RX_TX_IRQHandler
+    .long UART4_ERR_IRQHandler
+    .long 0
+    .long 0
+    .long CMP2_IRQHandler
+    .long FTM3_IRQHandler
+    .long DAC1_IRQHandler
+    .long ADC1_IRQHandler
+    .long I2C2_IRQHandler
+    .long CAN0_ORed_Message_buffer_IRQHandler
+    .long CAN0_Bus_Off_IRQHandler
+    .long CAN0_Error_IRQHandler
+    .long CAN0_Tx_Warning_IRQHandler
+    .long CAN0_Rx_Warning_IRQHandler
+    .long CAN0_Wake_Up_IRQHandler
+    .long SDHC_IRQHandler
+    .long ENET_1588_Timer_IRQHandler
+    .long ENET_Transmit_IRQHandler
+    .long ENET_Receive_IRQHandler
+    .long ENET_Error_IRQHandler
+    .long LPUART0_IRQHandler
+    .long TSI0_IRQHandler
+    .long TPM1_IRQHandler
+    .long TPM2_IRQHandler
+    .long USBHSDCD_IRQHandler
+    .long I2C3_IRQHandler
+    .long CMP3_IRQHandler
+    .long USBHS_IRQHandler
+    .long CAN1_ORed_Message_buffer_IRQHandler
+    .long CAN1_Bus_Off_IRQHandler
+    .long CAN1_Error_IRQHandler
+    .long CAN1_Tx_Warning_IRQHandler
+    .long CAN1_Rx_Warning_IRQHandler
+    .long CAN1_Wake_Up_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_DMA16_IRQHandler
+    IRQ DMA1_DMA17_IRQHandler
+    IRQ DMA2_DMA18_IRQHandler
+    IRQ DMA3_DMA19_IRQHandler
+    IRQ DMA4_DMA20_IRQHandler
+    IRQ DMA5_DMA21_IRQHandler
+    IRQ DMA6_DMA22_IRQHandler
+    IRQ DMA7_DMA23_IRQHandler
+    IRQ DMA8_DMA24_IRQHandler
+    IRQ DMA9_DMA25_IRQHandler
+    IRQ DMA10_DMA26_IRQHandler
+    IRQ DMA11_DMA27_IRQHandler
+    IRQ DMA12_DMA28_IRQHandler
+    IRQ DMA13_DMA29_IRQHandler
+    IRQ DMA14_DMA30_IRQHandler
+    IRQ DMA15_DMA31_IRQHandler
+    IRQ DMA_Error_IRQHandler
+    IRQ MCM_IRQHandler
+    IRQ FTFE_IRQHandler
+    IRQ Read_Collision_IRQHandler
+    IRQ LVD_LVW_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ WDOG_EWM_IRQHandler
+    IRQ RNG_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ I2S0_Tx_IRQHandler
+    IRQ I2S0_Rx_IRQHandler
+    IRQ UART0_RX_TX_IRQHandler
+    IRQ UART0_ERR_IRQHandler
+    IRQ UART1_RX_TX_IRQHandler
+    IRQ UART1_ERR_IRQHandler
+    IRQ UART2_RX_TX_IRQHandler
+    IRQ UART2_ERR_IRQHandler
+    IRQ UART3_RX_TX_IRQHandler
+    IRQ UART3_ERR_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ CMP1_IRQHandler
+    IRQ FTM0_IRQHandler
+    IRQ FTM1_IRQHandler
+    IRQ FTM2_IRQHandler
+    IRQ CMT_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT0_IRQHandler
+    IRQ PIT1_IRQHandler
+    IRQ PIT2_IRQHandler
+    IRQ PIT3_IRQHandler
+    IRQ PDB0_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ USBDCD_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTB_IRQHandler
+    IRQ PORTC_IRQHandler
+    IRQ PORTD_IRQHandler
+    IRQ PORTE_IRQHandler
+    IRQ SPI2_IRQHandler
+    IRQ UART4_RX_TX_IRQHandler
+    IRQ UART4_ERR_IRQHandler
+    IRQ CMP2_IRQHandler
+    IRQ FTM3_IRQHandler
+    IRQ DAC1_IRQHandler
+    IRQ ADC1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ CAN0_ORed_Message_buffer_IRQHandler
+    IRQ CAN0_Bus_Off_IRQHandler
+    IRQ CAN0_Error_IRQHandler
+    IRQ CAN0_Tx_Warning_IRQHandler
+    IRQ CAN0_Rx_Warning_IRQHandler
+    IRQ CAN0_Wake_Up_IRQHandler
+    IRQ SDHC_IRQHandler
+    IRQ ENET_1588_Timer_IRQHandler
+    IRQ ENET_Transmit_IRQHandler
+    IRQ ENET_Receive_IRQHandler
+    IRQ ENET_Error_IRQHandler
+    IRQ LPUART0_IRQHandler
+    IRQ TSI0_IRQHandler
+    IRQ TPM1_IRQHandler
+    IRQ TPM2_IRQHandler
+    IRQ USBHSDCD_IRQHandler
+    IRQ I2C3_IRQHandler
+    IRQ CMP3_IRQHandler
+    IRQ USBHS_IRQHandler
+    IRQ CAN1_ORed_Message_buffer_IRQHandler
+    IRQ CAN1_Bus_Off_IRQHandler
+    IRQ CAN1_Error_IRQHandler
+    IRQ CAN1_Tx_Warning_IRQHandler
+    IRQ CAN1_Rx_Warning_IRQHandler
+    IRQ CAN1_Wake_Up_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mkl26z4.s

@@ -0,0 +1,147 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MKL26Z4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MKL26Z4 NXP Microcontroller
+*/
+
+//     Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:
+//     o Redistributions of source code must retain the above copyright notice, this list
+//     of conditions and the following disclaimer.
+//     o Redistributions in binary form must reproduce the above copyright notice, this
+//     list of conditions and the following disclaimer in the documentation and/or
+//     other materials provided with the distribution.
+//     o Neither the name of the copyright holder nor the names of its
+//     contributors may be used to endorse or promote products derived from this
+//     software without specific prior written permission.
+//     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+//     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+//     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+//     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+//     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+//     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+//     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+//     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+//     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_IRQHandler
+    .long DMA1_IRQHandler
+    .long DMA2_IRQHandler
+    .long DMA3_IRQHandler
+    .long 0
+    .long FTFA_IRQHandler
+    .long LVD_LVW_IRQHandler
+    .long LLWU_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long SPI1_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long TPM0_IRQHandler
+    .long TPM1_IRQHandler
+    .long TPM2_IRQHandler
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT_IRQHandler
+    .long I2S0_IRQHandler
+    .long USB0_IRQHandler
+    .long DAC0_IRQHandler
+    .long TSI0_IRQHandler
+    .long MCG_IRQHandler
+    .long LPTMR0_IRQHandler
+    .long 0
+    .long PORTA_IRQHandler
+    .long PORTC_PORTD_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_IRQHandler
+    IRQ DMA1_IRQHandler
+    IRQ DMA2_IRQHandler
+    IRQ DMA3_IRQHandler
+    IRQ FTFA_IRQHandler
+    IRQ LVD_LVW_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ TPM0_IRQHandler
+    IRQ TPM1_IRQHandler
+    IRQ TPM2_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ I2S0_IRQHandler
+    IRQ USB0_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ TSI0_IRQHandler
+    IRQ MCG_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTC_PORTD_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/mkw41z4.s

@@ -0,0 +1,146 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from MKW41Z4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// MKW41Z4 NXP Microcontroller
+*/
+
+//     Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:
+//     o Redistributions of source code must retain the above copyright notice, this list
+//     of conditions and the following disclaimer.
+//     o Redistributions in binary form must reproduce the above copyright notice, this
+//     list of conditions and the following disclaimer in the documentation and/or
+//     other materials provided with the distribution.
+//     o Neither the name of the copyright holder nor the names of its
+//     contributors may be used to endorse or promote products derived from this
+//     software without specific prior written permission.
+//     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+//     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+//     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+//     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+//     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+//     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+//     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+//     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+//     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long DMA0_IRQHandler
+    .long DMA1_IRQHandler
+    .long DMA2_IRQHandler
+    .long DMA3_IRQHandler
+    .long 0
+    .long FTFA_IRQHandler
+    .long LVD_LVW_DCDC_IRQHandler
+    .long LLWU_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long SPI0_IRQHandler
+    .long TSI0_IRQHandler
+    .long LPUART0_IRQHandler
+    .long TRNG0_IRQHandler
+    .long CMT_IRQHandler
+    .long ADC0_IRQHandler
+    .long CMP0_IRQHandler
+    .long TPM0_IRQHandler
+    .long TPM1_IRQHandler
+    .long TPM2_IRQHandler
+    .long RTC_IRQHandler
+    .long RTC_Seconds_IRQHandler
+    .long PIT_IRQHandler
+    .long LTC0_IRQHandler
+    .long 0
+    .long DAC0_IRQHandler
+    .long 0
+    .long MCG_IRQHandler
+    .long LPTMR0_IRQHandler
+    .long SPI1_IRQHandler
+    .long PORTA_IRQHandler
+    .long PORTB_PORTC_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ DMA0_IRQHandler
+    IRQ DMA1_IRQHandler
+    IRQ DMA2_IRQHandler
+    IRQ DMA3_IRQHandler
+    IRQ FTFA_IRQHandler
+    IRQ LVD_LVW_DCDC_IRQHandler
+    IRQ LLWU_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ TSI0_IRQHandler
+    IRQ LPUART0_IRQHandler
+    IRQ TRNG0_IRQHandler
+    IRQ CMT_IRQHandler
+    IRQ ADC0_IRQHandler
+    IRQ CMP0_IRQHandler
+    IRQ TPM0_IRQHandler
+    IRQ TPM1_IRQHandler
+    IRQ TPM2_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ RTC_Seconds_IRQHandler
+    IRQ PIT_IRQHandler
+    IRQ LTC0_IRQHandler
+    IRQ DAC0_IRQHandler
+    IRQ MCG_IRQHandler
+    IRQ LPTMR0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ PORTA_IRQHandler
+    IRQ PORTB_PORTC_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/neom3.s

@@ -0,0 +1,145 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from LPC178x_7x_v0.8.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// Neo M3
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+    .long WWDT_IRQHandler
+    .long TIMER0_IRQHandler
+    .long TIMER1_IRQHandler
+    .long TIMER2_IRQHandler
+    .long TIMER3_IRQHandler
+    .long UART0_IRQHandler
+    .long UART1_IRQHandler
+    .long UART2_IRQHandler
+    .long UART3_IRQHandler
+    .long PWM1_IRQHandler
+    .long I2C0_IRQHandler
+    .long I2C1_IRQHandler
+    .long I2C2_IRQHandler
+    .long 0
+    .long SSP0_IRQHandler
+    .long SSP1_IRQHandler
+    .long 0
+    .long RTC_IRQHandler
+    .long EINT0_IRQHandler
+    .long EINT1_IRQHandler
+    .long EINT2_IRQHandler
+    .long EINT3_IRQHandler
+    .long ADC_IRQHandler
+    .long BOD_IRQHandler
+    .long USB_IRQHandler
+    .long CAN_IRQHandler
+    .long GPDMA_IRQHandler
+    .long I2S_IRQHandler
+    .long ETHERNET_IRQHandler
+    .long SDMMC_IRQHandler
+    .long MCPWM_IRQHandler
+    .long QEI_IRQHandler
+    .long 0
+    .long USB_NEED_CLK_IRQHandler
+    .long 0
+    .long UART4_IRQHandler
+    .long SSP2_IRQHandler
+    .long LCD_IRQHandler
+    .long GPIOINT_IRQHandler
+    .long PWM0_IRQHandler
+    .long EEPROM_IRQHandler
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+    IRQ WWDT_IRQHandler
+    IRQ TIMER0_IRQHandler
+    IRQ TIMER1_IRQHandler
+    IRQ TIMER2_IRQHandler
+    IRQ TIMER3_IRQHandler
+    IRQ UART0_IRQHandler
+    IRQ UART1_IRQHandler
+    IRQ UART2_IRQHandler
+    IRQ UART3_IRQHandler
+    IRQ PWM1_IRQHandler
+    IRQ I2C0_IRQHandler
+    IRQ I2C1_IRQHandler
+    IRQ I2C2_IRQHandler
+    IRQ SSP0_IRQHandler
+    IRQ SSP1_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ EINT0_IRQHandler
+    IRQ EINT1_IRQHandler
+    IRQ EINT2_IRQHandler
+    IRQ EINT3_IRQHandler
+    IRQ ADC_IRQHandler
+    IRQ BOD_IRQHandler
+    IRQ USB_IRQHandler
+    IRQ CAN_IRQHandler
+    IRQ GPDMA_IRQHandler
+    IRQ I2S_IRQHandler
+    IRQ ETHERNET_IRQHandler
+    IRQ SDMMC_IRQHandler
+    IRQ MCPWM_IRQHandler
+    IRQ QEI_IRQHandler
+    IRQ USB_NEED_CLK_IRQHandler
+    IRQ UART4_IRQHandler
+    IRQ SSP2_IRQHandler
+    IRQ LCD_IRQHandler
+    IRQ GPIOINT_IRQHandler
+    IRQ PWM0_IRQHandler
+    IRQ EEPROM_IRQHandler
+
+.size __isr_vector, .-__isr_vector

targets/device/nxp/qn908xc.s

@@ -0,0 +1,67 @@
+// Automatically generated file. DO NOT EDIT.
+// Generated by gen-device-svd.go from QN908XC.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP
+
+/*
+// QN9080C, QN9083C
+*/
+
+
+
+.syntax unified
+
+// This is the default handler for interrupts, if triggered but not defined.
+.section .text.Default_Handler
+.global  Default_Handler
+.type    Default_Handler, %function
+Default_Handler:
+    wfe
+    b    Default_Handler
+.size Default_Handler, .-Default_Handler
+
+// Avoid the need for repeated .weak and .set instructions.
+.macro IRQ handler
+    .weak  \handler
+    .set   \handler, Default_Handler
+.endm
+
+// Must set the "a" flag on the section:
+// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
+// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
+.section .isr_vector, "a", %progbits
+.global  __isr_vector
+__isr_vector:
+    // Interrupt vector as defined by Cortex-M, starting with the stack top.
+    // On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
+    // _stack_top and Reset_Handler.
+    .long _stack_top
+    .long Reset_Handler
+    .long NMI_Handler
+    .long HardFault_Handler
+    .long MemoryManagement_Handler
+    .long BusFault_Handler
+    .long UsageFault_Handler
+    .long 0
+    .long 0
+    .long 0
+    .long 0
+    .long SVC_Handler
+    .long DebugMon_Handler
+    .long 0
+    .long PendSV_Handler
+    .long SysTick_Handler
+
+    // Extra interrupts for peripherals defined by the hardware vendor.
+
+    // Define default implementations for interrupts, redirecting to
+    // Default_Handler when not implemented.
+    IRQ NMI_Handler
+    IRQ HardFault_Handler
+    IRQ MemoryManagement_Handler
+    IRQ BusFault_Handler
+    IRQ UsageFault_Handler
+    IRQ SVC_Handler
+    IRQ DebugMon_Handler
+    IRQ PendSV_Handler
+    IRQ SysTick_Handler
+
+.size __isr_vector, .-__isr_vector