4 Commits

Author	SHA1	Message	Date
luoliwoshang	6beb50b367	cl/instr:asmFull test case with multiple input & output	2025-08-21 23:44:46 +08:00
luoliwoshang	9e0c50dafe	cl/instr:asmFull test case with input only	2025-08-21 23:44:46 +08:00
luoliwoshang	f5d4f93ed7	ssa:inlineAsmFull	2025-08-21 23:44:46 +08:00
luoliwoshang	ae36ef4a0e	cl/instr:replace register & build constraints	2025-08-21 23:44:46 +08:00